Artificial neural networks (ANNs) constitute a class of flexible nonlinear models designed to mimic biological neural systems. In this entry, we introduce ANN using familiar econometric terminology and provide an overview of ANN modeling approach and its implementation methods. † Correspondence: Chung-Ming Kuan, Institute of Economics, Academia Sinica, 128 Academia Road, Sec. 2, Taipei 115, Taiwan; ckuan@econ.sinica.edu.tw. †† I would like to express my sincere gratitude to the editor, Professor Steven Durlauf, for his patience and constructive comments on early drafts of this entry. I also thank Shih-Hsun Hsu and Yu-Lieh Huang for very helpful suggestions. The remaining errors are all mine.

Artificial neural networks

An overview of the self-organizing map algorithm, on which the papers in this issue are based, is presented in this article.

The Self-Organizing Map

Generalized Sparse Matrix-Matrix Multiplication (SpGEMM) is a ubiquitous task in various engineering and scientific applications. However, inner product based SpGEMM introduces redundant input fetches for mismatched nonzero operands, while outer product based approach suffers from poor output locality due to numerous partial product matrices. Inefficiency in the reuse of either inputs or outputs data leads to extensive and expensive DRAM access. To address this problem, this paper proposes an efficient sparse matrix multiplication accelerator architecture, SpArch, which jointly optimizes the data locality for both input and output matrices. We first design a highly parallelized streaming-based merger to pipeline the multiply and merge stage of partial matrices so that partial matrices are merged on chip immediately after produced. We then propose a condensed matrix representation that reduces the number of partial matrices by three orders of magnitude and thus reduces DRAM access by 5.4x. We further develop a Huffman tree scheduler to improve the scalability of the merger for larger sparse matrices, which reduces the DRAM access by another 1.8x. We also resolve the increased input matrix read induced by the new representation using a row prefetcher with near-optimal buffer replacement policy, further reducing the DRAM access by 1.5x. Evaluated on 20 benchmarks, SpArch reduces the total DRAM access by 2.8x over previous state-of-the-art. On average, SpArch achieves 4x, 19x, 18x, 17x, 1285x speedup and 6x, 164x, 435x, 307x, 62x energy savings over OuterSpace, MKL, cuSPARSE, CUSP, and ARM Armadillo, respectively.

/pdf/sparch-efficient-architecture-for-sparse-matrix-25a3olbudk.pdf

SpArch: Efficient Architecture for Sparse Matrix Multiplication

Peak-to-average power-ratio (PAPR) reduction for OFDM systems is investigated in a probabilistic framework. A new constellation extension technique is developed whereby the data for each subcarrier are represented either by points in the original constellation or by extended points. An optimal representation of the OFDM signal is achieved by using a de-randomization algorithm where the conditional probability involved is handled by using the Chernoff bound and the evaluation of the many hyperbolic cosine functions involved is replaced by a tight upper bound for these functions. The proposed algorithm can be used by itself or be combined with a selective rotation technique described in the paper and with other known algorithms such as the coordinate descent optimization and selective mapping algorithms to achieve further performance enhancements at the cost of a slight increase in the computational complexity. When compared with other existing PAPR-reduction algorithms, the enhanced algorithm offers improved PAPR-reduction performance and improved computational complexity although, the transmit power is increased somewhat

/pdf/a-new-peak-to-average-power-ratio-reduction-algorithm-for-2twlktctqq.pdf

A New Peak-to-Average Power-Ratio Reduction Algorithm for OFDM Systems via Constellation Extension

We present a method for implementing high speed finite impulse response (FIR) filters using just registered adders and hardwired shifts. We extensively use a modified common subexpression elimination algorithm to reduce the number of adders. We target our optimizations to Xilinx Virtex II devices where we compare our implementations with those produced by Xilinx CoregenTM using Distributed Arithmetic. We observe up to 50% reduction in the number of slices and up to 75% reduction in the number of LUTs for fully parallel implementations. We also observed up to 50% reduction in the total dynamic power consumption of the filters. Our designs perform significantly faster than the MAC filters, which use embedded multipliers.

/pdf/fpga-implementation-of-high-speed-fir-filters-using-add-and-2layr8lbja.pdf

FPGA Implementation of High Speed FIR Filters Using Add and Shift Method

Investigates different architectures implementing bit-parallel constant-coefficient multiplication in FPGA structures. First, multiplierless multiplication (MM) architectures employing canonic sign digit (CSD) and sub-structure sharing methods are addressed, and a novel algorithm for the conversion from two's-complement to CSD representation is presented. In the second part of this paper, lookup table-based multiplication (LM) is investigated. Correspondingly, the usage of different memory modules and finding the optimal combination of the memory and adders are considered. The LM architecture also considers reduction of the address width for each memory cell and the possibility of memory sub-structure sharing. Finally, implementation results for the Xilinx XC4000 and Virtex families are presented. As a result, MM generally surpasses the LM architecture. However, the actual choice between these two architectures is coefficient- and input parameter-dependent.

Constant coefficient multiplication in FPGA structures

Most presented implementations of the exponential function confine to the single precision format. Increasing data width to the double precision format requires a different approach. The presented novel architecture employs three independent Look-Up Tables (LUTs) together with a short Taylor expansion exp(x)ap1+times. Implementation results show that the double precision exp() function implementation achieves huge performance with satisfactory accuracy, latency and FPGA area consumption.

FPGA Implementation of 64-Bit Exponential Function for HPC

In this paper different architectures for real time image constant coefficients convolutions are considered. Accordingly, look-up-table (LUT) based multiplication/convolution, LUT based distributed arithmetic (DA) convolution and multiplierless convolution (MC) implementations into FPGA structures has been investigated. In one result, the choice between these architectures depends on given coefficients values, however in most cases the MC preferable. Furthermore the change of coefficient values in real-time systems is also considered. This work is a contribution to worldwide intense research on developing reconfigurable and user dedicated custom computing machines (CCM).

Implementation image data convolutions operations in FPGA reconfigurable structures for real-time vision systems

This paper presents implementation of the double precision exponential function. A novel table-based architecture, together with short Taylor expansion, provides low latency (30 clock cycles) which is comparable to 32-bit implementations. Low area consumption of a single exp()module (roughtly 4% of XC4LX200) allows implementation of several parallel modules on a single FPGAs. The exp() function was implemented on the SGI RASC platform, thus external memory interface limitation allowed only a twin module parallelism. Each module is capable of processing at speed of 200 MHz with max. error of 1 ulp, RMSE equals 0,62. This implementation aims primarily to meet quantum chemistry's huge and strict requirements of precision and speed.

https://link.springer.com/content/pdf/10.1007/978-3-540-78610-8_28.pdf

Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs

FPGA implementation of the dynamic Huffman Encoder

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