Voltage and frequency scaling techniques that are based upon monitored data are provided. The techniques may be used to better manage the power and energy consumption of a processor in an embedded system, such as a cellular telephone, personal data assistant, smart device, or the like. The techniques may be used with processors that offer a performance monitoring capability. The performance monitor may monitor thread-level utilization at runtime. Instructions per cycle and memory references per cycle are example metrics that may be monitored by the performance monitor. The voltage and frequency scaling techniques may adjust the operating voltage and operating frequency of the processor based on the values of these two metrics. For example, the techniques may include accessing a voltage and frequency scheduler lookup table. The techniques may be employed with non-embedded systems, as well, embedded systems.

Performance monitoring based dynamic voltage and frequency scaling

The development of embedded systems requires the development of increasingly complex software and hardware platforms. Full system simulation makes it possible to run the exact binary embedded software including the operating system on a totally simulated hardware platform. Whereas most simulation environments do not support full system simulation, or do not use any hardware modeling techniques, or have combined different types of technology, SimSoC is developing a full system simulation architecture with an integrated approach relying only upon SystemC hardware modeling and transaction-level modeling abstractions (TLM) for communications. To simulate processors at reasonably high speed, SimSoC integrates instruction set simulators (ISS) as SystemC modules with TLM interfaces to the other platform components. The ISSpsilas use a variant approach of dynamic translation to run binary code. The dynamic translator uses pre-compiled code that consists of specialized functions for instruction execution, using partial evaluation techniques. It is generated by a configurable code generator, which makes it possible to tune the generated code to optimize simulation speed for the target software application.

/pdf/simsoc-a-systemc-tlm-integrated-iss-for-full-system-1pot1qlqdh.pdf

SimSoC: A SystemC TLM integrated ISS for full system simulation

Virtual machines (VM) are promising as system software in sensor networks. A major impediment to their widespread acceptance is their performance overhead. The compilation of VM byte code to native code improves performance, but increases the code's footprint and cost of code distribution. Thus, there is an important tradeoff between the cost of computing and the cost of communication due to code distribution. We describe a remote Just-In-Time compilation service that is effective in combining interpretation with native execution to arrive at an efficient hybrid execution configuration. The principles may be applied to any middleware that is used to develop applications for sensor networks.

Balancing computation and communication costs: The case for hybrid execution in sensor networks

Current trends in industry are leading towards the use of Java [5] as a programming language for implementing embedded and real-time applications. From the software engineering perspective, the Java environment is indeed a very attractive development framework. Object-oriented programming provides encapsulation of abstractions into objects that communicate through clearly defined interfaces. Dynamic loading eases the maintenance and improvement of complex applications with evolving requirements and functionality. Besides, Java provides built-in support for multi-threading.

/pdf/a-methodology-and-tool-support-for-generating-scheduled-4dlvw914eb.pdf

A Methodology and Tool Support for Generating Scheduled Native Code for Real-Time Java Applications

Virtual machines (VM) are promising as system software in sensor networks. A major impediment to their widespread acceptance is their performance over- head. Compiling VM bytecode to native code addresses this, but increases footprint and code distribution costs. Thus, there is an important tradeoff between cost of computing and cost of communication due to code distri- bution. In this paper, we describe a remote Just-In-Time (JIT) compilation service that is effective in combining interpretation with native execution to arrive at an efficient hybrid execution configuration. The principles apply to any middleware used to develop applications in sensor networks.

Bialancingv Computation and Communication Costs: The Case for Hybrid Execution in Sensor Networks

JCOD is a new compiler technology for appliances such as mobile phones or printers running embedded Java programs. Interpreted Java is sometimes too slow and one would like to compile bytecode into native code as this is achieved in JIT compilers on desktops. Our approach takes into account the memory and CPU constraints of the appliances. We have designed a distributed technology to efficiently detect "hot spots" of the application and compile them out of the appliance, on a network compile server that uses a lot of code size optimizations. This paper describes the different components and exhibits their flexibility. They can easily be upgraded independently or tailored for a specific kind of applications running on a given appliance.

JCOD: A Lightweight Modular Compilation Technology for Embedded Java

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JCOD: A Lightweight Modular Compilation Technology for Embedded Java