Resource-constrained IoT devices, such as sensors and actuators, have become ubiquitous in recent years. This has led to the generation of large quantities of data in real-time, which is an appealing target for AI systems. However, deploying machine learning models on such end-devices is nearly impossible. A typical solution involves offloading data to external computing systems (such as cloud servers) for further processing but this worsens latency, leads to increased communication costs, and adds to privacy concerns. To address this issue, efforts have been made to place additional computing devices at the edge of the network, i.e close to the IoT devices where the data is generated. Deploying machine learning systems on such edge computing devices alleviates the above issues by allowing computations to be performed close to the data sources. This survey describes major research efforts where machine learning systems have been deployed at the edge of computer networks, focusing on the operational aspects including compression techniques, tools, frameworks, and hardware used in successful applications of intelligent edge systems.

Machine Learning at the Network Edge: A Survey

Over the past few years, several applications have been extensively exploiting the advantages of deep learning, in particular when using convolutional neural networks (CNNs). The intrinsic flexibility of such models makes them widely adopted in a variety of practical applications, from medical to industrial. In this latter scenario, however, using consumer Personal Computer (PC) hardware is not always suitable for the potential harsh conditions of the working environment and the strict timing that industrial applications typically have. Therefore, the design of custom FPGA (Field Programmable Gate Array) solutions for network inference is gaining massive attention from researchers and companies as well. In this paper, we propose a family of network architectures composed of three kinds of custom layers working with integer arithmetic with a customizable precision (down to just two bits). Such layers are designed to be effectively trained on classical GPUs (Graphics Processing Units) and then synthesized to FPGA hardware for real-time inference. The idea is to provide a trainable quantization layer, called Requantizer, acting both as a non-linear activation for neurons and a value rescaler to match the desired bit precision. This way, the training is not only quantization-aware, but also capable of estimating the optimal scaling coefficients to accommodate both the non-linear nature of the activations and the constraints imposed by the limited precision. In the experimental section, we test the performance of this kind of model while working both on classical PC hardware and a case-study implementation of a signal peak detection device running on a real FPGA. We employ TensorFlow Lite for training and comparison, and use Xilinx FPGAs and Vivado for synthesis and implementation. The results show an accuracy of the quantized networks close to the floating point version, without the need for representative data for calibration as in other approaches, and performance that is better than dedicated peak detection algorithms. The FPGA implementation is able to run in real time at a rate of four gigapixels per second with moderate hardware resources, while achieving a sustained efficiency of 0.5 TOPS/W (tera operations per second per watt), in line with custom integrated hardware accelerators.

/pdf/quantization-aware-nn-layers-with-high-throughput-fpga-158y96cq.pdf

Quantization-Aware NN Layers with High-throughput FPGA Implementation for Edge AI

In the present century, where artificial intelligence and machine learning are regenerating the world, this paper takes inspiration from brain intelligence and explores new advanced computing known as Neuromorphic Computing. The energy efficiency and accuracy of the brain are remarkable and its retaining ability and grasping tendency are overwhelming. Motivated by this, our paper discusses this benchmarking technology i.e. neuromorphic computing and how it is optimizing machine learning techniques by developing Spiking Neural Networks (SNNs). Neuromorphic computing is constructing computers that have a commonality like the human brain and have all biological functionalities. This research paper discusses the recent neuromorphic systems and also presents the comparative analysis of the neuromorphic systems in which various research areas are discussed like image retrieval, forecasting, prediction and classification. Machine learning algorithms are applied everywhere nowadays and neuromorphic computing enables machine learning techniques to work in an efficient manner. This paper shows the power of neuromorphic computing as an essential epitome to existing Von-Neumann architecture and also aims to make the industry's future bright with more research work in this research area.

Evolution of Neuromorphic Computing with Machine Learning and Artificial Intelligence

The human brain can be viewed as an extremely power-efficient biological computer. As such, there have been many efforts to create brain-inspired processing systems to enable advances in low-power data processing. An example of brain-inspired processing architecture is the IBM TrueNorth Neurosynaptic System, a Spiking Neural Network architecture for deploying ultra-low power machine learning (ML) models and algorithms. For the first time ever, an advanced scalable computing architecture was demonstrated using 16 TrueNorth neuromorphic processors containing in aggregate over 16 million neurons. This system, called the NS16e, was used to demonstrate new ML techniques including the exploitation of optical and radar sensor data simultaneously, while consuming a fraction of the power compared to traditional Von Neumann computing architectures. The number of applications that have requirements for computing architectures that can operate in size, weight and power-constrained environments continues to grow at an outstanding pace. These applications include processors for vehicles, homes, and real-time data exploitation needs for intelligence, surveillance, and reconnaissance missions. This research included the successful exploitation of optical and radar data using the NS16e system. Processing performance was assessed, and the power utilization was analyzed. The NS16e system never used more than 15 W, with the contribution from the 16 TrueNorth processors utilizing less than 5 W. The image processing throughput was 16,000 image chips per second, corresponding to 1,066 image chips per second for each watt of power consumed.

Demonstrating Advanced Machine Learning and Neuromorphic Computing Using IBM’s NS16e

Field Programmable Gate Arrays (FPGA's) are being deployed in cloud data centers like Amazon Elastic compute cloud F1 instances for algorithmic acceleration to leverage the advantage of reconfigurability combined with high throughput and low power consumption of FPGA's and hence balancing the dynamic workloads. Gradient Descent is one such algorithm that is extensively used in core computation kernels to train the Machine Learning (ML) models. This paper proposes a custom-IP (Intellectual Property) for hardware acceleration of Gradient Descent Algorithm (GDA) which is designed by exploring the inherent concurrency of GDA. The IP incorporates the Very High-Speed Integrated Circuit Hardware Description Language (VHDL) based description of GDA and AXI4 stream interface for connectivity. The Custom-IP is flexible and reusable by tuning generics defined in the VHDL code. The IP is interfaced to a 32-bit MicroBlaze soft-core processor which acts as host and manages run-time along with other peripherals to form a System on Chip (SoC) in which the design is partitioned into fixed hardware and flexible software. The Hardware/Software Codesign results show the 5x improvement in performance when implemented on Artix XC7A100T-CSG324 FPGA when compared to software implementation.

Custom-IP for Gradient Descent Optimization based on Hardware/Software Co-design Paradigm

A newly invented, high performance, pod-based computer architecture, called Agile Condor (patent pending), has been designed and developed. Agile Condor is supporting autonomous operations by providing a platform for the innovative use of artificial intelligence, machine learning, and decision making algorithms upstream, near the information source, where the data is collected. In September 2016, experimental tests successfully demonstrated the ability to implement advanced neural networks and deep learning techniques on Agile Condor. We continue to use this new processing architecture, algorithms and bio-inspired computing methods to demonstrate existing, refine emerging and invent new artificial intelligence techniques that are highly applicable and needed for sensor platforms. For the first time ever, and in real-time, the system demonstrated: image processing, video processing and pattern recognition through the use of deep convolutional neural networks. Because of Agile Condor's modular architecture and performance characteristics, the system is providing flexible computational resources that will continue to bring new artificial intelligence (AI) capabilities closer to sensor platforms.

Utilizing high-performance embedded computing, agile condor, for intelligent processing: An artificial intelligence platform for remotely piloted aircraft

For the first time ever, advanced machine learning (ML) compute architectures, techniques, and methods were demonstrated on United States Geological Survey (USGS) optical imagery and Department of Defense (DoD) Synthetic Aperture Radar (SAR) imagery, simultaneously, using IBM’s new NS16e neurosynaptic processor board comprised of 16 TrueNorth chips. The Air Force Research Laboratory (AFRL) Information Directorate Advanced Computing and Communications Division continues to develop and demonstrate new bio-inspired computing algorithms and architectures, designed to provide advanced, ultra-low power, ground and airborne High-Performance Computing (HPC) solutions to meet operational and tactical, real-time processing needs for Intelligence, Surveillance, and Reconnaissance (ISR) missions on small form factor hardware, and in Size, Weight and Power (SWaP) constrained environments. With an average throughput of 16,000 inferences per second, the system provided a processing efficiency of 1,066 inferences per Watt. The NS16e power utilization never exceeded 15 Watts for this application. The contribution of power consumption from TrueNorth processors was bound to less than 5.5 Watts.

Low Power Computing and Simultaneous Electro-Optical/Radar Data Processing using IBM’s NS16e 16-chip Neuromorphic Hardware

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Utilizing high-performance embedded computing, agile condor, for intelligent processing: An artificial intelligence platform for remotely piloted aircraft

Demonstrating Advanced Machine Learning and Neuromorphic Computing Using IBM’s NS16e

Low Power Computing and Simultaneous Electro-Optical/Radar Data Processing using IBM’s NS16e 16-chip Neuromorphic Hardware