A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices

Wireless communication has led to an explosive growth of emerging consumer and military applications of radio frequency (RF), microwave and millimeter wave circuits and systems. Future personal (hand-held) and ground communications systems as well as communications satellites necessitate the use of highly integrated RF front-ends, featuring small size, low weight, high performance and low cost. Continuing chip scaling has contributed to the extent that off-chip, bulky passive RF components, such as high-Q inductors, ceramic and SAW filters, varactor diodes and discrete PIN diode switches, have become limiting. Micro-machining or MEMS technology is now rapidly emerging as an enabling technology to yield a new generation of high-performance RF-MEMS passives to replace these off-chip passives in wireless communication (sub)systems. This paper reviews the progress in RF-MEMS from a device and integration perspective. The worldwide state-of-the-art of RF-MEMS devices including switches, variable capacitors, resonators and filters are described. Next, it is stipulated how integration of RF-MEMS passives with other passives (as inductors, LC filters, SAW devices, couplers and power dividers) and, active circuitry (ASICs, RFICs) can lead to the so-called RF-MEMS system-in-a-package (RF-MEMS-SiP) modules. The evolution of the RF-MEMS-SiP technology is illustrated using IMEC's microwave multi-layer thin-film MCM-D technology which today already serves as a technology platform for RF-SiP.

https://iopscience.iop.org/article/10.1088/0960-1317/13/4/323/pdf

MEMS for wireless communications: 'from RF-MEMS components to RF-MEMS-SiP'

A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface; and a second wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface, wherein the metallic lines and the barrier line deposited on the surface of the second wafer are bonded with the metallic lines and the barrier line deposited on the surface of the first wafer to establish electrical connections between active IC devices on adjacent wafers and to form a barrier structure on the outer edge of the adjacent wafers.

Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack

A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.

Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same

This paper discusses the expectations for the development of radio-frequency systems-on-chip (RF-SoCs) that integrate RF, analog, and digital circuits, and the conditions under which they can be realized. Future RF systems will be increasingly large and complex. However, high integration technology is expected to reduce the circuit size, number of components, and total system cost. Over the past few years, rapid progress of scaled CMOS technology and the introduction of SiGe technology have improved the performance of silicon RF devices and circuits to meet the requirements for conventional RF applications. The RF-SoC, which may be said to be the ultimate goal for RF systems, is expected to improve silicon RF devices even further. However, before this is possible, strict requirements for system perfection, continuous cost reduction, ease of function and specification change, and process portability issues must be resolved. Difficulty in lowering power consumption of RF and analog circuits and of reducing the size of passive components and analog transistors diminish the appeal of the RF-SoC. The RF-SoC in deep submicrometer technology may be an unreasonable solution for some application areas. System-in-package may be one way to address this issue.

RF-SoC-expectations and required conditions

A structural shape has an injection molded, three-dimensional substrate composed of an electrically insulating polymer, polymer studs planarly arranged on the underside of the substrate and co-formed during injection molding, outside terminals formed on the polymer studs by a solderable end surface, interconnections fashioned at least on the underside of the substrate that connect the outside terminals to inside terminals, and at least one chip arranged on the substrate and whose terminals are electrically conductively connected to the inside terminals. The structural shape is suitable for single, few or multi chip module and unites the advantages of a ball grid array with the advantages of MID technology (Molded Interconnection Devices). The manufacture and metallization of the polymer studs can take place with minimal additional outlay in the framework of the method steps already required in the MID technology.

Polymer stud grid array

Multi-layer thin-film mcm-d for the integration of high performance wireless front-end systems

Single-package integration of complete transceivers based on a thin-film MCM technology (MCM-D) with integrated passives is demonstrated with a 67/spl times/65 mm/sup 2/ single-package front-end This front-end includes the RF blocks and two RF bandpass filters of a 5 GHz WLAN receiver

http://ieeexplore.ieee.org/iel5/6780/18154/00839797.pdf

Chip-package co-design of a 5 GHz RF front-end for WLAN

The Use of BCB and Photo-BCB Dielectric in MCM-D for High Speed Digital and Microwave Applications

The low temperature permanent wafer bonding is studied on the plasma enhanced chemical vapour deposited dielectrics. Three types of dielectric material (SiOx, SiOxNy, SiCxNy ) were prepared by the conventional CMOS interconnection process which includes the thermal annealing and chemical mechanical polishing step. The plasma treatment generated by different inert gas was evaluated to activate the dielectric surface prior to wafer bonding. The modified surface properties were characterized by using water wettability, hydrophilicity as well as the surface roughness. The obtained surface properties have been discussed with the interface bonding energy.

Bonding in the Low Temperature by Using Various Plasma Enhanced Chemical Vapour Deposition Dielectrics

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