This paper reviews emerging nonvolatile random access memories (RAM) in recent years. It first benchmarks ferroelectric RAM (FeRAM), phase change RAM (PCRAM), resistive RAM (ReRAM), and spin-torque-transfer magnetic RAM (STT-MRAM), discussing each RAM's features and its applications. Then current status of spintronics developments including not only STT-MRAM but also nonvolatile logic LSI is described, which are particularly suitable for working memory applications.

An Overview of Nonvolatile Emerging Memories— Spintronics for Working Memories

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing spintronic devices, especially magnetic tunnel junction (MTJ) devices with CMOS circuits, are discussed, and the current status of the MTJ-based VLSI computing paradigm is presented along with its prospects and remaining challenges.

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

Science and technology in the electronics area have always been driven by the development of materials with unique properties and their integration into novel device concepts with the ultimate goal to enable new functionalities in innovative circuit architectures. In particular, a shift in paradigm requires a synergistic approach that combines materials, devices and circuit aspects simultaneously. Here we report the experimental implementation of a novel nonvolatile memory cell that combines silicon nanowires with an organic ferroelectric polymer—PVDF-TrFE—into a new ferroelectric transistor architecture. Our new cell, the ferroelectric transistor random access memory (FeTRAM) exhibits similarities with state-of-the-art ferroelectric random access memories (FeRAMs) in that it utilizes a ferroelectric material to store information in a nonvolatile (NV) fashion but with the added advantage of allowing for nondestructive readout. This nondestructive readout is a result of information being stored in our cell...

FETRAM. An Organic Ferroelectric Material Based Novel Random Access Memory Cell

Existing nonvolatile ternary content-addressable-memory (nvTCAM) suffers from limited word-length (WDL), large write-energy ( $E_{W})$ and search-energy ( $E_{S})$ , and large cell area (A). This paper develops a 3T1R nvTCAM cell using a single multiple-level cell (MLC)-resistive RAM (ReRAM) device to achieve long WDL, lower $E_{W}$ and $E_{S}$ , and reduced cell area. Two peripheral control schemes were developed, dual-replica-row self-timed and invalid-entry power consumption suppression (IEPCS), for the suppression of dc current in 3T1R nvTCAM cells in order to reduce $E_{S}$ . Two versions of the IEPCS scheme were developed (basic and charge-recycle-controlled) to alter the tradeoff between area overhead and power consumption in the updating of invalid-bits. A $128~\text {b} \times 64$ b 3T1R nvTCAM macro was fabricated using back-end-of-line ReRAM under 90-nm CMOS process. The fabricated MLC-based 3T1R nvTCAM macro achieved sub-1-ns search-delay and sub-6-ns wake-up time with supply voltage of 1 V and WDL = 64 b.

A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing

Nonvolatile processor (NVP) attracts more and more attentions for its immunity to power loss in energy harvesting scenarios The overall performance of an NVP is determined by its sleep and wake-up speeds, which refer to how fast the NVP can turn itself off and on when a sudden power failure occurs To the best of our knowledge, this paper is the first work to improve the system-level sleep/wake-up speed of an energy harvesting NVP A hybrid CMOS/ferroelectric nonvolatile flip-flop (nvFF) and a high-speed voltage detector are designed and integrated in the proposed NVP to jointly minimize its sleep and wake-up time Measurement results demonstrate $46~\mu \text {s}$ wake-up time and $14~\mu \text {s}$ sleep time, which is up to 18 and 24 times speedup over existing works This approach not only improves the robustness of the NVP to power fluctuations but also brings significant advantages for better utilization of harvested energy

A Ferroelectric Nonvolatile Processor with 46 $\mu $ s System-Level Wake-up Time and 14 $\mu $ s Sleep Time for Energy Harvesting Applications

A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine

A circuit design assistance device (30) is provided with: an MTJ element identification unit (33) for identifying an MTJ element from circuit information indicative of the configuration of a spintronics integrated circuit; a magnetization reversal determination unit (35) for determining whether to cause a magnetization reversal, on the basis of MTJ element property information indicative of properties of an MTJ element and on the basis of an electrical current value supplied to the identified MTJ element; an approximation formula storage unit (37) for storing a first and second formula with which the relationship between the electrical current values supplied to the MTJ element and a time constant pertaining to magnetization is approximated on the basis of different theoretical models; and an operational information output unit (36) for outputting the resistance value of the MTJ element. The magnetization reversal determination unit has a first computing means for computing the time constant needed for the magnetization reversal on the basis of the first and second formulae, and a second computing means for computing a magnetization reversal probability from the computed time constant. The magnetization reversal determination unit determines whether to cause a magnetization reversal on the basis of the magnetization reversal probability. This makes it possible to swiftly and precisely simulate the operation of an integrated circuit that includes an MTJ element.

Circuit design assistance device, method, and program

A memory circuit (11) includes: a memory cell (MCij) including a variable-resistance element in which a resistance value varies substantially between two levels; a resistance-voltage conversion circuit that converts the resistance value of a memory cell (MCij) to be read into a data voltage; a reference circuit (RC1) including a series circuit of a variable-resistance element and a linear resistor, the variable-resistance element including substantially the same configuration as the configuration of the variable-resistance element included in the memory cell MCij and being set to a lower resistance of two levels; a reference voltage conversion circuit that converts the resistance value of the reference circuit (RCi) into a reference voltage; and a sense amplifier (SA) that determines data stored in the memory cell (MCij) by comparing the data voltage with the reference voltage.

Memory circuit provided with variable-resistance element

A magnetoresistive effect element (100) has a recording layer (10) that contains a ferromagnetic body, a barrier layer (20) layered on the recording layer (10), and a reference layer (30) layered on the barrier layer (20), the reference layer (30) containing a ferromagnetic body The reference layer (30) has a magnetization component substantially fixed substantially in the in-plane direction The recording layer (10) includes: a first magnetization fixed region (11) having a magnetization component essentially fixed in substantially the in-plane direction; a second magnetization fixed region (12) having a magnetization component essentially fixed in the direction opposite that of the magnetization component of the first magnetization fixed region (11); and a magnetization free region (13) positioned between the first magnetization fixed region (11) and the second magnetization fixed region (12), the magnetization free region (13) having a magnetization component capable of inverting in substantially the in-plane direction The wire width of a fine wire constituting a part of the recording layer (10) is 40 nm or less The film thickness of the recording layer (10) is 40 nm or less and is equivalent to half to twice the wire width

Magnetoresistive effect element and magnetic memory device

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