https://www2.econ.iastate.edu/tesfatsi/DeepLearningInNeuralNetworksOverview.JSchmidhuber2015.pdf

Deep learning in neural networks

An information processing system having signal processors that are interconnected by processing junctions that simulate and extend biological neural networks. As shown in the figure, each processing junction receives signals from one signal processor and generates a new signal to another signal processor. The response of each processing junction is determined by internal junction processes and is continuously changed with temporal variation in the received signal. Different processing junctions connected to receive a common signal from a signal processor respond differently to produce different signals to downstream signal processors. This transforms a temporal pattern of a signal train of spikes into a spatio-temporal pattern of junction events and provides an exponential computational power to signal processors. Each signal processing junction can receive a feedback signal from a downstream signal processor so that an internal junction process can be adjusted to learn certain characteristics embedded in received signals.

Dynamic synapse for signal processing in neural networks

Understanding how the brain manages billions of processing units connected via kilometers of fibers and trillions of synapses, while consuming a few tens of Watts could provide the key to a completely new category of hardware (neuromorphic computing systems). In order to achieve this, a paradigm shift for computing as a whole is needed, which will see it moving away from current “bit precise” computing models and towards new techniques that exploit the
stochastic behavior of simple, reliable, very fast, 
low-power computing devices embedded in intensely recursive architectures. In this paper we summarize how these objectives will be pursued in the Human Brain Project.

The Human Brain Project and neuromorphic computing.

A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

A Voltage Mode Memristor Bridge Synaptic Circuit with Memristor Emulators

The aim of this paper is to propose a new classification approach of artificial neural networks hardware. Our motivation behind this work is justified by the following two arguments: first, during the last two decades a lot of approaches have been proposed for classification of neural networks hardware. However, at present there is not a clear consensus on classification criteria and performances. Second, with the evolution of the microelectronic technology and the design tools and techniques, new artificial neural networks (ANNs) implementations have been proposed, but they are not taken into consideration in the existing classification approaches of ANN hardware. In this paper, we propose a new approach for classification of neural networks hardware. The paper is organized in three parts: in the first part we review most of existing approaches proposed in the literature during the period 1990---2010 and show the advantages and disadvantages of each one. In the second part, we propose a new classification approach that takes into account most of consensual elements in one hand and in the other hand it takes into consideration the evolution of the design technology of integrated circuits and the design techniques. In the third part, we review examples of neural hardware achievements from industrial, academic and research institutions. According to our classification approach, these achievements range from standard chips to VLSI ASICs, FPGA and embedded systems on chip. Finally, we enumerate design issues that are still posed. This could help to give new directions for future research work.

A new classification approach for neural networks hardware: from standards chips to embedded systems on chip

A general purpose neurocomputer, SYNAPSE-1, which exhibits a multiprocessor and memory architecture is presented. It offers wide flexibility with respect to neural algorithms and a speed-up factor of several orders of magnitude — including learning. The computational power is provided by a 2-dimensional systolic array of neural signal processors. Since the weights are stored outside these NSPs, memory size and processing power can be adapted individually to the application needs. A neural algorithms programming language, embedded in C++ has been defined for the user to cope with the neurocomputer. In a benchmark test, the prototype of SYNAPSE-1 was 8000 times as fast as a standard workstation.

Multiprocessor and Memory Architecture of the Neurocomputer SYNAPSE-1

A general purpose neurocomputer, SYNAPSE-1, is presented which exhibits a multi processor and memory architecture. It offers wide flexibility with respect to neural algorithms and a speed-up factor of several orders of magnitude -- including learning. The computational power is provided by a 2-dimensional systolic array of neural signal processors. Since the weights are stored outside these NSPs memory size and processing power can be adapted individually to the applicational needs. A neural Algorithms Programming Language, embedded in C ++, has been defined for the user to cope with the neurocomputer. In a benchmark test the prototype of SYNAPSE-1 was 8000 times as fast as a standard workstation.

The paper describes the general purpose neurocomputer SYNAPSE-1 which has been developed in cooperation between Siemens Munich and the University of Mannheim. This system contains one of the most powerful processors available for neural algorithms, the neuro signal processor MA16. The prototype system executes a test algorithm 8000 times as fast as a Sparc-2 workstation. This processing speed has been achieved by using a system architecture which is optimally adapted to the general structure of neural algorithms. It is a systolic array of MA16 processors embedded in a multiprocessor system of general purpose microprocessors. >

/pdf/synapse-1-a-high-speed-general-purpose-parallel-1x2hh13ty8.pdf

SYNAPSE-1: a high-speed general purpose parallel neurocomputer system

whereas virtual round-table conferencing needs at the sender’s side to find a person’s head, cut it from the background, code it and at the receiver’s side to decode and insert it at the round-table by means of geometric transformations (figure below shows virtual round table) Hence, a vision processor has to support image processing, coding/decoding and 3D graphics Accordingly, a representative body of algorithms from these 3 vision fields was analysed with respect to computational power, elementary instructions and data types needed It was found that scalar, vector and matrix constitute the main data types, and a set of 205 visionbased instructions for vector and matrix types was defined Architectural studies led to a parallel array of 16 processing elements (PE) executing the vision instructions on vector and matrix data, as well as to special cache architectures adapted to the new data types For decoding of instructions, a set of controllers had to be introduced that would deliver control bits to the amount of what full-fledged general-purpose processors use to generate, but at a decade lower power level Finally, starting off from the OAK DSP and its Ccompiler, a programming model extending C by some vision based semantics, but keeping the C syntax was thought to be adequate for the user It is the set of 205 application-specific instructions and its computing and memory architecture that make the vision processor a generic one (see [1] for recent alternatives) In the following, only the functional highlights are reported

A 53-GOPS programmable vision processor for processing, coding-decoding and synthesizing of images

A 0.13 /spl mu/m CMOS add-compare-select unit (ACSU) is presented allowing for a maximum data rate of 2.8 Gb/s. A modified bit-level pipelining scheme combined with a new state metric representation has been implemented using single-rail DOMINO logic and static CMOS gates. The adaptation of architecture and circuit technique results in a compact energy-efficient design. The 0.5mm/sup 2/ chip consumes 970mW at 2 Gb/s (VDD = 1.2 V) and 2.2 W at 2.8 Gb/s (VDD = 1.5 V).

A 2.8 Gb/s, 32-state, radix-4 Viterbi decoder add-compare-select unit

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Multiprocessor and Memory Architecture of the Neurocomputer SYNAPSE-1

Multiprocessor and Memory Architecture of the Neurocomputer SYNAPSE-1

SYNAPSE-1: a high-speed general purpose parallel neurocomputer system

A 53-GOPS programmable vision processor for processing, coding-decoding and synthesizing of images

A 2.8 Gb/s, 32-state, radix-4 Viterbi decoder add-compare-select unit