E. Kaltalioglu
Infineon Technologies
5 Papers
90 Citations
E. Kaltalioglu is an academic researcher from Infineon Technologies. The author has contributed to research in topics: CMOS & Copper interconnect. The author has an hindex of 4, co-authored 5 publications. Previous affiliations of E. Kaltalioglu include IBM.
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Papers
65nm cmos technology for low power applications
An L. Steegen,Renee T. Mo,Randy W. Mann,M.-C. Sun,Manfred Eller,G. Leake,Dirk Vietzke,A. Tilke,Fernando Guarin,A. Fischer,T. Pompl,J. Greg Massey,A. Vayshenker,W.L. Tan,A. Ebert,W. Lin,W. Gao,J. Lian,J.-P. Kim,P. Wrschka,J.-H. Yang,Atul C. Ajmera,R. Knoefler,Y.-W. Teh,F.F. Jamin,Jae-Eun Park,K. Hooper,C. Griffin,P. Nguyen,V. Klee,V. Ku,Christopher V. Baiocco,Gregory M. Johnson,L. Tai,J. Benedict,S. Scheer,H. Zhuang,V. Ramanchandran,G. Matusiewicz,Y.-H. Lin,Y.K. Siew,F. Zhang,L.S. Leong,S.L. Liew,K.C. Park,K.-W. Lee,D.H. Hong,S.-M. Choi,E. Kaltalioglu,S.O. Kim,M. Naujok,M. Sherony,Andy Cowley,Alvin G. Thomas,J. Sudijohno,T. Schiml,J.-H. Ku,I. Yang +57 more
- 05 Dec 2005
TL;DR: In this paper, a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 12V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0676mum2 and 054mum 2 SRAM cells, optimized for performance and density, respectively.
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A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology
Sujatha Sankaran,S. Arai,R. Augur,M. Beck,G. A. Biery,T. Bolom,Griselda Bonilla,O. Bravo,Kaushik Chanda,M. Chae,F. Chen,Larry Clevenger,Stephan A. Cohen,A. Cowley,P. Davis,James J. Demarest,J.P. Doyle,Christos D. Dimitrakopoulos,L. Economikos,Daniel C. Edelstein,Mukta G. Farooq,R. G. Filippi,John A. Fitzsimmons,Nicholas C. M. Fuller,Stephen M. Gates,Stephen E. Greco,Alfred Grill,Stephan Grunow,R. Hannon,K. Ida,D. Jung,E. Kaltalioglu,M. Kelling,T. Ko,Kaushik A. Kumar,C. Labelle,H. Landis,Michael Lane,William F. Landers,Myoung-Bum Lee,W. Li,Eric G. Liniger,X. Liu,James R. Lloyd,W. Liu,Naftali E. Lustig,K. Malone,S. Marokkey,G. Matusiewicz,Paul S. McLaughlin,P. V. McLaughlin,Sanjay Mehta,I. Melville,K. Miyata,B. Moon,Satya V. Nitta,D. Nguyen,L. Nicholson,D. Nielsen,P. Ong,Kaushal Patel,V. Patel,Wan-jae Park,John G. Pellerin,Shom Ponoth,Kevin S. Petrarca,David L. Rath,Darryl D. Restaino,S. Rhee,E.T. Ryan,H. Shoba,Andrew H. Simon,Eva E. Simonyi,Thomas M. Shaw,Terry A. Spooner,Theodorus E. Standaert,J. Sucharitaves,C. Tian,H. Wendt,J. Werking,Johnny Widodo,L. Wiggins,Robert L. Wisnieff,T. H. Ivers +83 more
- 01 Dec 2006
TL;DR: In this article, a high performance 45nm BEOL technology with proven reliability is presented, which has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly developed advanced PecVD ultralow-k (ULK) porous Si-coh (k =2.4).
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Reliability Challenges in Copper Metallizations arising with the PVD Resputter Liner Engineering for 65nm and Beyond
Armin Fischer,Oliver Aubel,Jason Gill,Tom C. Lee,Baozhen Li,Cathryn Christiansen,F. Chen,Matthew Angyal,T. Bolom,E. Kaltalioglu +9 more
- 01 Apr 2007
TL;DR: In this paper, the authors investigated the influence of liners on the reliability of 65nm copper metallizations for two different deposition sequences and found that the use of resputter liners in the 65nm generation turned out to change the via-voiding failure mode qualitatively from voiding at the very via-bottom to void nucleation at mid-half of the via.
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•Proceedings Article
A 0.18um Dual Gate (3.5nm/6.8nm) CMOS Technology with Copper Metallurgy for Logic, SRAM, and Analog Applications
B. Agarwala,M. Armacost,S. Biesemans,L. Burrell,B. Chen,K. Han,D. Harmon,J. Heidenreich,K. Holloway,Terence B. Hook,S. Kapur,T. Kebede,D. Kiesling,P. Kim,G. Matusiewicz,J. Lukaitis,Phung T. Nguyen,N. Prabhakara,Stewart E. Rauch,N. Rovedo,L. Saraf,J. Slinkman,H. Tang,Robert C. Wong,S. Yankee,K.-H. Allers,A. Augustin,G. Brase,E. Demm,C. Derby,G. Friese,F. Grellner,E. Kaltalioglu,Mark Hoinkis,Chih-Yung Lin,Reinhard Mahnkopf,O. Prigge,Thomas Schafbauer,T. Schiml,Klaus Schruefer,S. Srinivasan,M. Stetter,G. Unger,R. Zoeller +43 more
- 01 Jan 1999
TL;DR: In this article, a 0.18-m technology for logic and SRAM applications at 1.8V, with 3.3V 110 and 2-3V analog function, is described.
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•Proceedings Article
64nm pitch interconnects: Optimized for designability, manufacturability and extendibility
Cindy Goldberg,S. H. Park,B. Y. Kim,S. B. Law,Bassem Hamieh,Ju-Hwan Jung,Bomsoo Kim,S. H. Rhee,M. Oh,M. Mobley,E. Laffosse,A. Kim,Alvin G. Thomas,P. Malinge,T. Fryxell,K. J. Lim,I.S. Park,B. Bahierathan,F. Wu,B. Erenturk,W. C. Jeon,Hyuk-soon Choi,Yong-young Park,Hoonki Kim,T. Q. Chen,S. Thibaut,C. Niu,J. Zhang,R. G. Filippi,E. Kaltalioglu,R. Achanta,P.-C Wang,H. Yang,J. P. Geronimi,F. Pagette,Vikrant Chauhan,A. Ogino,Ravi Prakash Srivastava,R. Koshy,Frieder H. Baumann,A. Simon,Joyeeta Nag,T. Cheng,John A. Fitzsimmons,Wei-Tsu Tseng,Y. Lin,Z. Sun,T. Bolom,T.-M Ko,Larry Clevenger,J. Kim,J. Sudijono,Ron Sampson +52 more
- 11 Jun 2013
TL;DR: In this paper, a 64nm pitch integration and materials strategy is presented to enable aggressive groundrules and extendibility for multi-node insertions, and the resulting ground rules and process module have been “plugged in” to multiple technology nodes without re-development needed.
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