This paper describes the Sandbridge Sandblaster real-time software-defined radio platform. Specifically, we describe the SB3011 system-on-a-chip multiprocessor. We describe the software development system that enables real-time execution of communications and multimedia applications. We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding. Each processor core achieves 600MHz at 0.9V operation while typically dissipating 75mW in 90nm technology. The entire chip typically dissipates less than 500mW at 0.9V.

/pdf/the-sandbridge-sb3011-platform-5cxzqgmq19.pdf

The sandbridge SB3011 platform

Embedded digital signal processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor's architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor's programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications.

A Low-Power Multithreaded Processor for Software Defined Radio

A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

Multithreaded processor with multiple concurrent pipelines per thread

This paper describes the Sandbridge Sandblaster real-time software defined radio platform. Specifically we describe the SB301I system on a chip multiprocessor. We describe the software development system that enables real-time execution of communications and multimedia applications. We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding. All results presented are from completely implemented systems from RF through baseband

The sandbridge SB3011 SDR platform

A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting the bits of the input operands and setting a carry into each of a plurality of reduction adders to one. The reduction unit can be used in conjunction with m parallel multipliers to quickly perform dot products and other vector operations with either saturating or wrap-around arithmetic.

Processor reduction unit for accumulation of multiple operands with or without saturation

Parallel saturating multioperand adders significantly improve the performance of global system for mobile (GSM) speech coders by giving compilers and assembly language programmers the ability to parallelize loops containing saturating dot products, while maintaining GSM compliant results. This paper presents four designs for parallel saturating multioperand adders. These designs have at most one carry-propagate adder on their critical delay path, yet produce the same results that would be obtained if the additions were performed serially with saturation after each addition. The four parallel designs offer tradeoffs in terms of area, worst case delay, and dot product latency. Compared to a 5-input serial design, the 5-input parallel designs have delays up to 3.51 times shorter.

/pdf/design-alternatives-for-parallel-saturating-multioperand-4cdg0hklfd.pdf

Design alternatives for parallel saturating multioperand adders

We discuss the hardware and software challenges in building a 2 Mbit per second wireless battery powered communications device. Of primary importance is power dissipation. To achieve aggressive power targets, a host of new techniques are required at all levels of the design hierarchy. Techniques for parallelizing saturating arithmetic will become important because of the software optimizations they enable. Highly configurable programmable structures will enable multiprotocol SOC solutions. To program complex SOCs, new compiler techniques will be required. Hardware implementations will need to be intimately aware of these software techniques. In particular both signal processing code written in C and control code written in Java will drive new compilation techniques to enable broadband 3G wireless systems.

https://ieeexplore.ieee.org/iel5/7350/19935/00923132.pdf

Towards a very high bandwidth wireless battery powered device

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Design alternatives for parallel saturating multioperand adders

Towards a very high bandwidth wireless battery powered device