Symbolic simulation has been proposed as a way to formally verify the correct operation of an MOS circuit. By allowing nonground expressions as values, a symbolic simulator avoids the complexity of exhaustive simulation. The symbolic expressions chosen for initializing the state- and input-variables must cover all valid test cases while avoiding those that violate circuit constraints. In this paper, we present a new approach to symbolic simulation-based verification that hinges on the use of parametric forms of Boolean expressions. A parametric form of a Boolean expression E is an equivalent expression in which the variables in E are expressed in terms of expressions over new variables called parametric variables. In our approach, Boolean expressions representing the operating constraints on the circuit node values are first converted into the parametric form, and the resulting parametric expressions are used as initial (symbolic) node values prior to each simulation step. In addition to the proposal to use the parametric form, we make the following additional contributions. We present a new method for generating the parametric form of a Boolean expression that exploits (among other things) the structural recursion involved in defining commonly used arithmetic/relational operators. Our method generates parametric forms that are more compact, as well as more balanced in terms of term-sizes than generated by the following existing methods: Boole's, Lowenheim's, and the generalized cofactor method. We have also developed a variety of example-specific techniques to deal with circuit constraints. All algorithms discussed in this paper have been implemented in a verification prototype system. Experimental results obtained using the COSMOS symbolic simulator are also reported. >

Efficient symbolic simulation-based verification using the parametric form of Boolean expressions

We describe a new method to simplify combinational circuits while preserving the set of all possible values (that is, the range) on the outputs. This method is performed iteratively and on the fly while building BDDs of the circuits. The method is composed of three steps; 1) identifying a cut in the circuit, 2) identifying a group of nets within the cut, 3) replacing the logic driving the group of nets in such away that the range of values for the entire cut is unchanged and, hence, the range of values on circuit outputs is unchanged. Hence, we parameterize the circuit in such away that the range is preserved and the representation is much more efficient than the original circuit. Actually, these replacements are not done in terms of logic gates but in terms of BDDs directly. This is allowed by a new generalized parametric representation algorithm to deal with both input and output variables at the same time.We applied this method to combinational equivalence checking and the experimental results show that this technique outperforms an existing related method which replaces one logic net at a time. We also proved that the previous method is a special case of ours. This technique can be applied to various other problem domains such as symbolic simulation and image computation in model checking.

Simplifying Circuits for Formal Verification Using Parametric Representation

A task frequently encountered in digital circuit design is the solution of a two-valued Boolean equation of the form h(X,Y,Z)=1, where h: B_2^(k+m+n)→ B_2 and X,Y, and Z are binary vectors of lengths k, m, and n, representing inputs, intermediary values, and outputs, respectively. The resultant of the suppression of the variables Y from this equation could be written in the form g(X,Z)=1 where g: B_2^(k+n)→ B_2. Typically, one needs to solve for Z in terms of X, and hence it is unavoidable to resort to ‘big’ Boolean algebras which are finite (atomic) Boolean algebras larger than the two-valued Boolean algebra. This is done by reinterpreting the aforementioned g(X,Z) as g(Z): B_(2^K)^n→ B_(2^K ), where B_(2^K ) is the free Boolean algebra FB(X_1,X_2…….X_k ), which has K= 2^k atoms, and 2^K elemnets. This paper describes how to unify many digital specifications into a single Boolean equation, suppress unwanted intermediary variables Y, and solve the equation g(Z)=1 for outputs Z (in terms of inputs X) in the absence of any information about Y. The paper uses a novel method for obtaining the parametric general solutions of the ‘big’ Boolean equation g(Z)=1. The parameters used do not belong to B_(2^K ) but they belong to the two-valued Boolean algebra B_2, also known as the switching algebra or propositional algebra. To achieve this, we have to use distinct independent parameters for each asserted atom in the Boole-Shannon expansion of g(Z). The concepts and methods introduced herein are demonsrated via several detailed examples, which cover the most prominent type among basic problems of digital circuit design.

https://www.ijmems.in/assets//29-ijmems-17-012-vol.-3%2c-no.-4%2c-404%E2%80%93428%2c-2018.pdf

Digital Circuit Design Utilizing Equation Solving over ‘Big’ Boolean Algebras

In the simplest setting, one represents a boolean function using expressions over variables, where each variable corresponds to a function input. So-called parametric representations, used to represent a function in some restricted subspace of its domain, break this correspondence by allowing inputs to be associated with functions. This can lead to more succinct representations, for example when using binary decision diagrams (BDDs). Here we introduce Universal Boolean Functional Vectors (UBFVs), which also break the correspondence, but done so such that all input vectors are accounted for. Intelligent choice of a UBFV can have a dramatic impact on BDD size; for instance we show how the hidden weighted bit function can be efficiently represented using UBFVs, whereas without UBFVs BDDs are known to be exponential for any variable order. We show several industrial examples where the UBFV approach has a huge impact on proof performance, the "killer app" being floating point addition, wherein the wide case-split used in the state-of-the-art approach is entirely done away with, resulting in 70-fold reduction in proof runtime. We give other theoretical and experimental results, and also provide two approaches to verifying the crucial "universality" aspect of a proposed UBFV. Finally, we suggest several interesting avenues of future research stemming from this program.

/pdf/universal-boolean-functional-vectors-2ws22wvj9q.pdf

Universal boolean functional vectors

This note presents an alternate approach to solving the inverse problem of logic by applying a decomposition technique based on Boolean equations.

Comments on "Equational Logic

A method has been investigated for the synthesis of memoryless logical networks using a restricted repertoire of functional modules. The method is based on the reduced general solution to a generalized system of Boolean equations (BE) as applied to the decomposition of Boolean functions. The aim of the synthesis is to obtain the most constrained circuit having at most two levels of gating. The constraints take the form of single input variables or constant logic levels applied to the inputs of the first level gate. This is achieved by assembling a set of constraint equations which are then a part of the generalized system of BE. The method is then tested on some synthesis examples of single and multiple output functions in terms of the NAND and (WOS) modules.

A Computer Algorithm for the Synthesis of Memoryless Logic Circuits

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A Computer Algorithm for the Synthesis of Memoryless Logic Circuits