E. Cartier
GlobalFoundries
12 Papers
118 Citations
E. Cartier is an academic researcher from GlobalFoundries. The author has contributed to research in topics: Gate dielectric & High-κ dielectric. The author has an hindex of 8, co-authored 12 publications.
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Papers
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
Michael P. Chudzik,Bruce B. Doris,R. Mo,Jeffrey W. Sleight,E. Cartier,C. DeWan,Dae-Gyu Park,Huiming Bu,Wesley C. Natzle,W. Yan,C. Ouyang,K. Henson,Diane C. Boyd,S. Callegari,R. Carter,D. Casarotto,Michael A. Gribelyuk,M. Hargrove,Wei He,Y. Kim,Barry P. Linder,Naim Moumen,Vamsi Paruchuri,James H. Stathis,Michelle L. Steen,A. Vayshenker,X. Wang,Sufi Zafar,Takashi Ando,Ryosuke Iijima,Mariko Takayanagi,Vijay Narayanan,Richard Wise,Y. Zhang,R. Divakaruni,Mukesh Khare,Tze-Chiang Chen +36 more
- 12 Jun 2007
TL;DR: In this article, a gate-first integration of band-edge high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented.
88
Patent
Low power circuit structure with metal gate and high-k dielectric
Bruce B. Doris,E. Cartier,Barry Linder,Vijay Narayanan,Vamsi Paruchuri +4 more
- 07 Aug 2007
TL;DR: In this article, the PFET and NFET devices have high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers, and the terminal electrodes of both types of devices can be butted with each other in direct physical contact.
32
Patent
Threshold and flatband voltage stabilization layer for field effect transistors with high permittivity gate oxides
Nestor A. Bojarczuk,E. Cartier,Martin M. Frank,Evgeni Gousev,Supratik Guha,Vijay Narayanan +5 more
- 14 May 2004
TL;DR: In this article, an insulating interlayer for use in complementary metal oxide semiconductor (CMOS) that prevents unwanted shifts in threshold voltage and flatband voltage is provided, which is particularly useful in stabilizing the threshold voltage of p-type field effect transistors.
21
Dual work function metal gate CMOS using CVD metal electrodes
Vijay Narayanan,Alessandro C. Callegari,Fenton R. McFeely,K. Nakamura,Paul C. Jamison,Sufi Zafar,E. Cartier,An L. Steegen,Victor Ku,Phung T. Nguyen,K. Milkove,Cyril Cabral,Michael A. Gribelyuk,C. S. Wajda,Y. Kawano,Dianne L. Lacey,Li Yulong,E. Sikorski,F. Duch,H. Ng,C. Wann,Rajarao Jammy,Meikei Ieong,Ghavam G. Shahidi +23 more
- 15 Jun 2004
TL;DR: In this paper, a dual work function metal gated MOSFET with CVD TaSiN, W and Re has been fabricated on HfO/sub 2/. T/sub inv/ as low as 1.46 nm with appropriate Vts and sub-threshold slopes 90 mV/decade or better.
20
Patent
MOS device having a passivated semiconductor-dielectric interface
Paul M. Solomon,Douglas A. Buchanan,E. Cartier,Kathryn W. Guarini,Fenton R. McFeely,Huiling Shang,John J. Yourkas +6 more
- 16 Jan 2001
TL;DR: In this paper, a MOS structure processed to have a semiconductor-dielectric interface that is passivated to reduce the interface state density is presented, and atomic hydrogen diffusion can be achieved by subjecting such an electrode to hydrogen plasma, forming the electrode of an aluminum-tungsten alloy in the presence of hydrogen, and implanting atomic hydrogen into the electrode.
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