Effect of gate engineering in double-gate MOSFETs for analog/RF applications

In this paper, for the first time, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications. For this purpose, the suitability of the device for low-power applications is investigated by extracting the threshold voltage of the device using a transconductance change method and a constant current method. Furthermore, the effects of uniform and Gaussian drain doping profile on dc characteristics and analog/RF performances are investigated for different channel lengths. A highly doped layer is placed in the channel near the source–channel junction, and this decreases the width of the depletion region, which improves the ON-current ( ${I_{\rm{\scriptscriptstyle ON}}}$ ) and the RF performance. Furthermore, the circuit-level performance assessment is done by implementing a common source amplifier using the H-DGTFET; a 3-dB roll-off frequency of 230.11 GHz and a unity-gain frequency of 5.4 THz were achieved.

Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping

To overcome the problem of fabrication complexity and to reducei the cost of microelectronic devices, a new concept of dual-material control gate with dual-oxide tunnel field-effect transistor is investigated. A stack gate approach is applied to reduce the width of tunneling barrier at source–channel junction. Use of dual oxides at source–channel interface provides improved capacitive coupling, which enhances the on-state current. The entire gate segment has been partitioned into three parts, namely tunnel gate $$(M_1)$$, control gate $$(M_2)$$ and auxiliary gate $$(M_3)$$ with different work functions such as $$\phi _{1}$$, $$\phi _{2}$$ and $$\phi _{3}$$. In this context, to keep dual-work functionality, the feasible combinations of these work functions are adopted. Technology computer- aided design (TCAD) simulations of these proposed combinations of work functions along with dual oxides provide better results for the combinations of $$(\phi _1=\phi _3<\phi _2)$$. In addition, comparison between these combinations on the basis of analog/RF performance is done in this work. This work shows improved analog/RF parameters such as $$g_\text {m}, C_\text {gs}, C_\text {gd}, f_\text {T}$$ and TFP, and linearity parameters including $$g_\text {m3}, \text {VIP3, IIP3}$$ and $$\text {IMD3}$$ for the proposed device DMDODG-TFET (dual-material dual-oxide double-gate TFET). The use of this proposed device structure reduces the ambipolar behavior and subthreshold swing $$(18.5\,\text {mV}/\text {deacde})$$, and enhances the on-current [$$3.6\times 10^{-5}\,(A/\upmu \text {m})$$] significantly, making it suitable for analog/RF and linearity applications.

Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance

In this paper, for the first time, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications. For this purpose, the suitability of the device for low-power applications is investigated by extracting the threshold voltage of the device using a transconductance change method and a constant current method. Furthermore, the effects of uniform and Gaussian drain doping profile on dc characteristics and analog/RF performances are investigated for different channel lengths. A highly doped layer is placed in the channel near the source-channel junction, and this decreases the width of the depletion region, which improves the ON-current (ION) and the RF performance. Fur- thermore, the circuit-level performance assessment is done by implementing a common source amplifier using the H-DGTFET; a 3-dB roll-off frequency of 230.11 GHz and a unity-gain frequency of 5.4 THz were achieved.

Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping Shylendra Ahish, Dheeraj Sharma, Yernad Balachandra Nithin Kumar, and Moodabettu Harishchandra Vasantha

DC characteristics and analog/RF performance of novel polarity control GaAs-Ge based tunnel field effect transistor

In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance (gm) and very low output conductance, the RF/analog performances of MCFET-voltage gain (A VI) and early voltage (V EA) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (fT), due to the large total input gate capacitances (C GG). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and fT. The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.

Analog/RF Performance of Multichannel SOI MOSFET

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Analog/RF Performance of Multichannel SOI MOSFET