Loihi is a 60-mm2 chip fabricated in Intels 14-nm process that advances the state-of-the-art modeling of spiking neural networks in silicon. It integrates a wide range of novel features for the field, such as hierarchical connectivity, dendritic compartments, synaptic delays, and, most importantly, programmable synaptic learning rules. Running a spiking convolutional form of the Locally Competitive Algorithm, Loihi can solve LASSO optimization problems with over three orders of magnitude superior energy-delay-product compared to conventional solvers running on a CPU iso-process/voltage/area. This provides an unambiguous example of spike-based computation, outperforming all known conventional solutions.

Loihi: A Neuromorphic Manycore Processor with On-Chip Learning

Guided by brain-like ‘spiking’ computational frameworks, neuromorphic computing—brain-inspired computing for machine intelligence—promises to realize artificial intelligence while reducing the energy requirements of computing platforms. This interdisciplinary field began with the implementation of silicon circuits for biological neural routines, but has evolved to encompass the hardware implementation of algorithms with spike-based encoding and event-driven representations. Here we provide an overview of the developments in neuromorphic computing for both algorithms and hardware and highlight the fundamentals of learning and hardware frameworks. We discuss the main challenges and the future prospects of neuromorphic computing, with emphasis on algorithm–hardware codesign. The authors review the advantages and future prospects of neuromorphic computing, a multidisciplinary engineering concept for energy-efficient artificial intelligence with brain-inspired functionality.

Towards spike-based machine intelligence with neuromorphic computing.

Traditional von Neumann computing systems involve separate processing and memory units. However, data movement is costly in terms of time and energy and this problem is aggravated by the recent explosive growth in highly data-centric applications related to artificial intelligence. This calls for a radical departure from the traditional systems and one such non-von Neumann computational approach is in-memory computing. Hereby certain computational tasks are performed in place in the memory itself by exploiting the physical attributes of the memory devices. Both charge-based and resistance-based memory devices are being explored for in-memory computing. In this Review, we provide a broad overview of the key computational primitives enabled by these memory devices as well as their applications spanning scientific computing, signal processing, optimization, machine learning, deep learning and stochastic computing. This Review provides an overview of memory devices and the key computational primitives for in-memory computing, and examines the possibilities of applying this computing approach to a wide range of applications.

Memory devices and applications for in-memory computing

The distributed network of receptors, neurons, and synapses in the somatosensory system efficiently processes complex tactile information. We used flexible organic electronics to mimic the functions of a sensory nerve. Our artificial afferent nerve collects pressure information (1 to 80 kilopascals) from clusters of pressure sensors, converts the pressure information into action potentials (0 to 100 hertz) by using ring oscillators, and integrates the action potentials from multiple ring oscillators with a synaptic transistor. Biomimetic hierarchical structures can detect movement of an object, combine simultaneous pressure inputs, and distinguish braille characters. Furthermore, we connected our artificial afferent nerve to motor nerves to construct a hybrid bioelectronic reflex arc to actuate muscles. Our system has potential applications in neurorobotics and neuroprosthetics.

A bioinspired flexible organic artificial afferent nerve

Dense crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing massively-parallel and highly energy-efficient neuromorphic computing systems. We first revie...

https://www.tandfonline.com/doi/pdf/10.1080/23746149.2016.1259585

Neuromorphic computing using non-volatile memory

Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm 2 , and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities.

/pdf/a-reconfigurable-on-line-learning-spiking-neuromorphic-wul33mru5c.pdf

A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses.

Neuromorphic hardware emulates dynamics of biological neural networks in electronic circuits offering an alternative to the von Neumann computing architecture that is low-power, inherently parallel, and event-driven. This hardware allows to implement neural-network based robotic controllers in an energy-efficient way with low latency, but requires solving the problem of device variability, characteristic for analog electronic circuits. In this work, we interfaced a mixed-signal analog-digital neuromorphic processor ROLLS to a neuromorphic dynamic vision sensor (DVS) mounted on a robotic vehicle and developed an autonomous neuromorphic agent that is able to perform neurally inspired obstacle-avoidance and target acquisition. We developed a neural network architecture that can cope with device variability and verified its robustness in different environmental situations, e.g., moving obstacles, moving target, clutter, and poor light conditions. We demonstrate how this network, combined with the properties of the DVS, allows the robot to avoid obstacles using a simple biologically-inspired dynamics. We also show how a Dynamic Neural Field for target acquisition can be implemented in spiking neuromorphic hardware. This work demonstrates an implementation of working obstacle avoidance and target acquisition using mixed signal analog/digital neuromorphic hardware.

/pdf/obstacle-avoidance-and-target-acquisition-for-robot-229llnzuky.pdf

Obstacle Avoidance and Target Acquisition for Robot Navigation Using a Mixed Signal Analog/Digital Neuromorphic Processing System

Spike-based neuromorphic learning circuits typically represent their synaptic weights as voltages, and convert them into post-synaptic currents so that they can be integrated by their afferent silicon neuron. This voltage-to-current conversion is often done using a single transistor. This results in an exponential (for weak-inversion) or quadratic (for strong inversion) non-linear transformation which severely restricts the type of learning algorithms that can be implemented. To overcome this problem we propose a range of solutions that perform a linear transformation fro m weight voltage to synaptic current, simplifying the implementation of a spike-based learning rules. We demonstrate the application of these conversion circuits using current-mode integrators that produce alpha-functions with biologically realistic temporal dynamics and amplitudes that are linearly proportional to the synaptic weights. The circuits proposed are low-power, and can be integrated in a wide range of spike-based learning framework s that have been recently proposed. We describe the advantages and disadvantages of the various solutions proposed and validate them with circuit simulation results.

Wide dynamic range weights and biologically realistic synaptic dynamics for spike-based learning circuits

Neurorobotics aims to use models of biological neural systems to design efficient and adaptive robotic controllers. For complex, perception-driven behaviors, such neuronal controllers require substantial computational time and resources when simulated in software. However, these controllers can be implemented in an efficient way using neuromorphic hardware systems. Here, we present two neural-dynamic architectures, implemented with a neuromorphic VLSI device for controlling simple robot behaviors: a reactive collision avoidance strategy and a spatio-temporal feature extraction to estimate relative visual motion. We demonstrate how these architectures may be realized in neuromorphic robotic agents

https://www.zora.uzh.ch/id/eprint/132657/1/Neurally-inspired_neuromophic_controllers.pdf

Neurally-inspired robotic controllers implemented on neuromorphic hardware

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A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses.

Obstacle Avoidance and Target Acquisition for Robot Navigation Using a Mixed Signal Analog/Digital Neuromorphic Processing System

Wide dynamic range weights and biologically realistic synaptic dynamics for spike-based learning circuits

Neurally-inspired robotic controllers implemented on neuromorphic hardware