Energy-proportional designs would enable large energy savings in servers, potentially doubling their efficiency in real-life use. Achieving energy proportionality will require significant improvements in the energy usage profile of every system component, particularly the memory and disk subsystems.

/pdf/the-case-for-energy-proportional-computing-4un8a5n8c1.pdf

The Case for Energy-Proportional Computing

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC or CPD provides a fast-path that avoids host protocol processing for most large multipacket messages, greatly accelerating data communication. The INIC or CPD also assists the host for those message packets that are chosen for processing by host software layers. A communication control block (CCB) for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The CCB can be passed back to the host for message processing by the host. The INIC or CPD contains hardware circuits configured for protocol processing that can perform that specific task faster than the host CPU. One embodiment includes a processor providing transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

Intelligent Network Interface System and Method for Protocol Processing

A Network Interface device (NI device) coupled to a host computer receives a multi-packet message from a network (for example, the Internet) and DMAs the data portions of the various packets directly into a destination in application memory on the host computer. The address of the destination is determined by supplying a first part of the first packet to an application program such that the application program returns the address of the destination. The address is supplied by the host computer to the NI device so that the NI device can DMA the data portions of the various packets directly into the destination. In some embodiments the NI device is an expansion card added to the host computer, whereas in other embodiments the NI device is a part of the host computer.

Obtaining a destination address so that a network interface device can write network data without headers directly into host memory

A device includes a converged input/output controller that includes a physical target storage media controller, a physical network interface controller and a gateway between the storage media controller and the network interface controller, wherein gateway provides a direct connection for storage traffic and network traffic between the storage media controller and the network interface controller.

Methods and systems for converged networking and storage

Provided herein are methods and systems for improved storage strategies for use of collections of storage resources, such as solid state drives, including in connection with a converged networking and storage node that may be used for virtualization of a collection of physically attached and/or network-connected storage resources.

Methods and systems for data storage using solid state drives

In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.

Network direct memory access

In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

Data Flow Control Within and Between DMA Channels

Direct memory access controller and method for the same

An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm2 die is implemented in a 65nm 8M process with low-power design techniques. Circuits to improve system performance under power constraints are discussed

Cores and Integrated Memory and I/O Subsystems

In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

DMA controller configured to process control descriptors and transfer descriptors

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