The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

https://www.mdpi.com/2079-9292/10/1/79/pdf

Carbon nanotube field effect transistor (Cntfet) and resistive random access memory (rram) based ternary combinational logic circuits

In this paper, the design of ternary logic gates (standard ternary inverter, ternary NAND, ternary NOR) based on carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) is proposed. Ternary logic has emerged as a very promising alternative to the existing binary logic systems owing to its energy efficiency, operating speed, information density and reduced circuit overheads such as interconnects and chip area. The proposed design employs active load RRAM and CNTFET instead of large resistors to implement ternary logic gates. The proposed ternary logic gates are then utilised to carry out basic arithmetic functions and is extendable to implement additional complex functions. The proposed ternary gates show significant advantages in terms of component count, chip area, power consumption, energy consumption and dense fabrication. The results demonstrate the advantage of the proposed models with a reduction of 50% in transistor count for the STI, TNAND and TNOR logic gates. For THA and THS arithmetic modules 65.11% reduction in transistor count is observed while for TM design, around 38% reduction is observed. In this work, we aim to demonstrate the viability of RRAM in the design of ternary logic systems, thus the focus is mainly on obtaining the proper functionality of the proposed design. Also the proposed logic gates show a very small variation in power consumption and energy consumption with variation in process parameters, temperature, output load, supply voltage and operating frequency. For simulations, HSPICE tool is used to verify the authenticity of the proposed designs. The ternary half adder, ternary half subtractor and ternary multiplier circuits are then implemented utilising the proposed gates and validated through simulations.

/pdf/carbon-nanotube-and-resistive-random-access-memory-based-2ye0r9uxp2.pdf

Carbon Nanotube and Resistive Random Access Memory Based Unbalanced Ternary Logic Gates and Basic Arithmetic Circuits

This paper proposes a highly stable and low power 6-T static random access memory (SRAM) cell design using a gate-all-around carbon nanotube field effect transistor (GAA-CNTFET). The 6-T SRAM cell is designed and analyzed in HSPICE for different performance metrics viz. SNM, read SNM, write SNM, delay, and leakage power for both the top gate CNTFET and the GAA-CNTFET. The effect of variation of the power supply voltage on the leakage current is also presented, and it was found that the GAA-CNTFET accounts for low power dissipation at higher supply voltage. The 6-T SRAM cell is analyzed for different flat band conditions of the p-type CNTFET taking flatband of the n-type as constant, which is called a dual flat band voltage technique. Through simulations, it is found that by increasing the flatband voltage of a p-type CNTFET, the SRAM gives better performance. The dual flatband variation technique is compared with dual chirality technique, and it is observed that both techniques give the same results.

Design and analysis of a gate-all-around CNTFET-based SRAM cell

In-memory computing seeks to minimize data movement and alleviate the memory wall by computing in-situ, in the same place that the data is located. One of the key emerging technologies that promises to enable such computing-in-memory is spin-transfer torque magnetic tunnel junction (STT-MTJ). This paper proposes AM4, a combined STT-MTJ-based Content Addressable Memory (CAM), Ternary CAM (TCAM), approximate matching (similarity search) CAM (ACAM), and in-memory Associative Processor (AP) design, inspired by the recently announced Samsung MRAM crossbar. We demonstrate and evaluate the performance and energy-efficiency of the AM4-based AP using a variety of data intensive workloads. We show that an AM4-based AP outperforms state-of-the-art solutions both in performance (with the average speedup of about 10 ×) and energy-efficiency (by about 60 × on average). 

AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing

This paper proposes a novel Hamming distance tolerant content-addressable memory (HD-CAM) for energy-efficient in-memory approximate matching applications. HD-CAM exploits NOR-type based static associative memory bitcells, where we add circuitry to enable approximate search with programmable tolerance. HD-CAM implements approximate search using matchline charge redistribution rather than its rise or fall time, frequently employed in state-of-the-art solutions. HD-CAM was designed in a 65 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm { \text {n} \text {m} }$ </tex-math></inline-formula> 1.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm { \text {V}}$ </tex-math></inline-formula> CMOS technology and evaluated through extensive Monte Carlo simulations. Our analysis shows that HD-CAM supports robust operation under significant process variations and changes in the design parameters, enabling a wide range of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mismatch threshold (tolerable Hamming distance) levels and pattern lengths. HD-CAM was functionally evaluated for virus DNA classification, which makes HD-CAM suitable for hardware acceleration of genomic surveillance of viral outbreaks, such as Covid-19 pandemics.

/pdf/hamming-distance-tolerant-content-addressable-memory-hd-cam-2l7me0hr.pdf

Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification

The carbon nanotube field-effect transistor (CNFET) is emerging as one of the most promising alternatives to complementary metal---oxide---semiconductor (CMOS) transistors due to its one-dimensional (1-D) band structure, low off-current capability, near-ballistic transport operation, high stability, and low power consumption. This paper presents the design of a CNFET-based ternary content-addressable memory (TCAM) cell and rigorously analyzes its performance in terms of power---delay product (PDP) and static noise margin (SNM). The effect of variations of the chiral vector on the performance of the TCAM cell is also comprehensively investigated. While selecting the chirality, SNM, PDP, and search time are considered as figures of merit. In this TCAM cell design, we apply the same chirality for all CNFETs of the same type. Extensive HSPICE simulations have been performed for computation of performance parameters using the Stanford University CNFET model. Comparison of CNFET- and CMOS-based TCAM cells has been carried out at the 16-nm technology node. The results show that the CNFET-based TCAM cell exhibits significant improvements of PDP, i.e., by 38 % during write operation and 98 % during search operation, and 53 % in SNM, compared with its CMOS counterpart. It is also observed that the best chirality for the TCAM cell design is (22, 19, 0) or (10, 19, 0) from the point of view of SNM and PDP, respectively.

Design and performance analysis of a CNFET-based TCAM cell with dual-chirality selection

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Design and performance analysis of a CNFET-based TCAM cell with dual-chirality selection