A road vehicle has a number of micro-computer modules interconnected via a communication bus that allows messages and data to be transmitted mambiguously. Typically, the micro-computer modules are assigned to provide control of the power transmission, engine fuelling and ignition.The priority bus system can be physically configured with either electrical conductors or optical fibres. With electrical cables the bus terminal points may be completed using inductive couplers or electro-optic couplers and the cable can be in the form of a twisted pair. The fibre optical conductor utilises opto-electrical terminals.Data may be multiplexed through the bus system using a system of priority control for access by the different processors

Operating communication bus network for processors

PROBLEM TO BE SOLVED: To allow the other outside equipment to execute the other data processing by using the other data bus when one outside equipment occupies a data bus, and to allow the outside equipment connected with each data bus to time-sequentially share a memory for data. SOLUTION: This device is provided with a main storage device 30, and a three-way interface device 200 for reading and writing data between the main storage device 30 and the data base A, writing and reading data between the main storage device 30 and a data base B, and operating data transfer between the two data buses A and B. The input and output of the two data buses A and B is time-sequentially controlled by the three-way interface device 200. COPYRIGHT: (C)1999,JPO

Data processor and system constitution method

PROBLEM TO BE SOLVED: To reduce the data processing load on a controller on data transfer. SOLUTION: A bi-directional interface 13 which is connected to a data bus 11 and inputs/outputs data, a bi-directional interface part 16 which is connected to a data bus 12 and inputs/outputs data, internal data buses 15a and 15b connected to the interface parts 13 and 16 and a command register 17a which temporarily records a control instruction D1 for controlling the input/output of the interface parts 13 and 16 and the internal data buses 15a and 15b and the writing/reading of FIFO memories 14a and 14b are provided. At the time of transferring data between the data buses 11 and 12, the control instruction D1 is written into the command register 17a.

Interface device and data processing system

PURPOSE:To improve remarkably substantial transmission efficiency and operating efficiency of a system by providing processing priority to a text to be transmitted based on the urgency on ship navigation and executing processing in order from a text having a higher priority. CONSTITUTION:The data to be transmitted by a text edition circuit 31 is collected into the test in the unit of packets and the urgency of processing is set in response to the content. After an edited text is written in a transmission data queue memory 32 corresponding to the set priority code, the text is led to a data highway 15 in the higher priority order by a transmission processing circuit 33 and transmitted to designated stations 11-14. A text edition circuit 31 of the reception station assembles and edits the return text in response to the analyzed content, the return text is stored in the transmission data queue memory 32 by the priority, the return text is extracted in the high priority order from the transmission processing circuit 33 and transmitted to the transmission station.

Data communication processing system for ship

PURPOSE:To improve the reliability of a communication interface circuit by using two buffer circuits for emergency and normal uses and giving priority to the communication data stored in the emergency buffer circuit to execute with no delay the real time processes such as the cancel of the preceding data, etc. CONSTITUTION:A data deciding circuit 6 decides whether the communication data received by a communication interface 1 is equal to the emergency or normal communication data. The normal communication data is stored temporarily to a reception buffer circuit 2A; while the emergency communication data is stored temporarily to a reception buffer circuit 2B respectively. The stored emergency and normal communication data are transmitted to a terminal device 5 via an interruption request line INT-L and a control bus CT-BUS respectively. Then a data bus D-BUS is used to read those data. An interruption is applied for the emergency communication data to eliminate delays. Thus the modulation is prevented for the overall working of a system. This improves the reliability of a communication interface circuit.

Communication interface circuit

PURPOSE:To make a preferential processing possible to improve the use efficiency of a data buffer, by storing communication data in the data buffer designated by the communication order from the transmission-side processor and by processing this data in accordance with communication purposes. CONSTITUTION:A control device 30 for communication between processors is provided with data buffers 60-80 which are adapted to transmission data different in communication purpose, respectively, and the communication order from transmission-side processors 11-1n and 21-2m is analyzed by a data buffer controller 50, and one data buffer corresponding to the communication purpose out of data buffers 60-80 is selected by this analysis, and transmission data from transmission-side processors 11-1n and 21-2m are stored temporarily. When transmission data is stored in some of buffers 60-80, this transmission data is taken out and is transmitted to receiving-side processors 11-1n and 21-2m designated by the communication order. Consequently, transmission data requiring a severe real time processing is processed preferentially, and the use efficiency of data buffers is improved.

Data buffer controlling system

PURPOSE:To increase a data transfer speed, by operating both buses in parallel, when controlling a data transfer of a processor group coupled with a high-speed bus, and a processor group coupled with a low speed bus. CONSTITUTION:Processors CP1-CPn are coupled with a high speed bus IPBH, processors NP1-NPn are coupled with a low-speed bus IPBL, and both the buses are coupled with a data transfer controller IPC, and are divided into two systems by the device IPC. The device IPC is provided with a high-speed bus access control means and a low-speed bus access control means, and when data is transferred between CPi (i=1-n) and NPk (k=1-n), both the bus access control means are operated in parallel. In this way, the transfer time is shortened.

Data transfer controller

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Data buffer controlling system

Data transfer controller