Presented in this paper are: 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise. In particular, lower bounds on a) circuit speed f/sub c/ and supply voltage V/sub dd/; b) transition activity t in presence of noise; c) dynamic energy dissipation; and d) total (dynamic and static) energy dissipation are derived. A surprising result is that in a scenario where dynamic component of power dissipation dominates, the supply voltage for minimum energy operation (V/sub dd, opt/) is greater than the minimum supply voltage (V/sub dd, min/)for reliable operation. We then propose noise tolerance via coding to approach the lower bounds on energy dissipation. We show that the lower bounds on energy for an off-chip I/O signaling example are a factor of 24/spl times/ below present day systems. A very simple Hamming code can reduce the energy consumption by a factor of 3/spl times/, while Reed-Muller (RM) codes give a 4/spl times/ reduction in energy dissipation.

Toward achieving energy efficiency in presence of deep submicron noise

This paper presents a much improved, highly accurate yet efficient crosstalk noise model, the 2-/spl pi/ model, and applies it to noise-constrained interconnect optimizations. Compared with previous crosstalk noise models of similar complexity, our 2-/spl pi/ model takes into consideration many key parameters, such as coupling locations (near-driver or near-receiver), and the coarse distributed RC characteristics for victim net. Thus, it is very accurate (less than 6% error on average compared with HSPICE simulations). Moreover, our model provides simple closed-form expressions for both peak noise amplitude and noise width, so it is very useful for noise-aware layout optimizations. In particular we demonstrate its effectiveness in two applications: (i) optimization rule generation for noise reduction using various interconnect optimization techniques, (ii) simultaneous wire spacing to multiple nets for noise constrained interconnect minimization.

/pdf/improved-crosstalk-modeling-for-noise-constrained-1hqq77gasg.pdf

Improved crosstalk modeling for noise constrained interconnect optimization

Coupled noise analysis has become a critical issue for deep-submicron, high performance design. In this paper, we present, ClariNet, an industrial noise analysis tool, which was developed to efficiently analyze large, high performance processor designs. We present the overall approach and tool flow of ClariNet and discuss three critical large-processor design issues which have received limited discussion in the past. First, we present how the driver gates of a coupled interconnect network are represented with accurate linear models. Second, we show how to speed the analysis of large designs by using noise filters based on reduced interconnect representations and then pruning the nets coupled to a signal net. Third, we show how to incorporate logic and timing correlations into noise analysis to reduce its pessimism. We present the results from several industrial circuits, including a large high performance microprocessor design and a DSP design.

ClariNet: a noise analysis tool for deep submicron design

The performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. In this paper we present a closed-form crosstalk noise model with accuracy comparable to that of SPICE for an arbitrary ramp input. We also develop a simplified delay model for estimating delays on coupled RC lines considering input slew times for both agressor and victim lines. We then apply our model along with SPICE simulation to perform various studies of delay uncertainty in coupled interconnects. With respect to the effects of changing aggressor slew time on victim delay (i.e., delay variation), we observe that the victim delay is worst when the aggressor is switching very fast (e.g., step input). For local interconnects the delay variation (change in victim delay with varying input slew) can be as high as 70%. On the other hand, delay variation is around 10% for global interconnects. We also observe that the difference between minimum and maximum delay (i.e., delay uncertainty) decreases significantly as slew times are increased. Delay uncertainty on the victim wire is high for global wires as compared to local wires, a consequence of differing ratios of coupling to parallel-plate capacitance, and wire to load capacitance. We believe that our noise and delay analytical models form an effective basis for methodologies that lead to less over-design and guard-banding in high-performance system designs.

/pdf/noise-and-delay-uncertainty-studies-for-coupled-rc-4wftfubq83.pdf

Noise and delay uncertainty studies for coupled RC interconnects

In coupling delay computation, a Miller factor of more than 2/spl times/ may be necessary to account for active coupling capacitance when modeling the delay of deep submicron circuitry in the presence of active coupling capacitance. We propose an efficient method to estimate this factor such that the delay response of a decoupling circuit model can emulate the original coupling circuit. Under the assumptions of zero initial voltage, equal charge transfer, and 0.5V/sub DD/ as the switching threshold voltage, an upper bound of 3/spl times/ for maximum delay and a lower bound of -1/spl times/ for minimum delay can be proven. Efficient Newton-Raphson iteration is also proposed as a technique for computing the Miller factor or effective capacitance. This result is highly applicable to crosstalk coupling delay calculation in deep submicron gate-level static timing analysis. Detailed analysis and approximation are presented. SPICE simulations are demonstrated to show high correlation with these approximations.

Miller factor for gate-level coupling delay calculation

Noise analysis and avoidance is an increasingly critical step in deep submicron design Ever increasing requirements on performance have led to widespread use of dynamic logic circuit families and its other derivatives These aggressive circuit families trade off noise margin for timing performance making them more susceptible to noise failure and increasing the need for noise analysis Currently, noise analysis is performed either through circuit or timing simulation or through model order reduction These techniques in use are still inefficient for analyzing massive amount of interconnect data found in present day integrated circuits This paper presents efficient techniques for estimation of coupled noise in on-chip interconnects This noise estimation metric is an upper bound for RC circuits, being similar in spirit to Elmore delay in timing analysis Such an efficient noise metric is especially useful for noise criticality pruning and physical design based noise avoidance techniques

Efficient coupled noise estimation for on-chip interconnects

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Devgan

Author Tools

Chat about Author

Papers

Efficient coupled noise estimation for on-chip interconnects