In an SSD controller reading from flash memory, subsequent to failure of an initial soft-decision decoding attempt based on a nominal LLR, soft-decision re-decoding attempts are made using compensated LLR soft-decision information sets, pre-calculated at respective read-equilibrium points corresponding to mean shifts and variance change in the actual charge-state distributions of the flash memory channel. According to embodiment, soft-decision re-decoding attempts are performed without a retry read, or overlapped with one or more retry reads. By overlapping re-decoding with one or more retry reads, the probability of successful decoding increases, the need for further retry reads diminishes, and throughput is improved. The LLR compensation becomes very effective over a large number of retry reads, improving decoding reliability and achieving close to optimal bit error rates, even in the presence of large channel variation.

Soft-decision compensation for flash channel variation

The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.

Physical page, logical page, and codeword correspondence

A storage device includes a transducer head including a first write element configured to write data at a first write width and a second write element configured to write data at a second write width less than the first write width. According to one implementation, the first write element writes data at a first linear density and to alternating data tracks and the second write element writes data at a second linear density and to data tracks interlaced with the alternating data tracks.

Interlaced magnetic recording

According to one embodiment, a memory controller that controls a non-volatile semiconductor memory including a memory cell of 3 bits/cell includes a controller that extracts bits which becomes an error caused by the movement to the adjacent threshold voltage distribution from a first bit and a second bit of data to be written in each of the memory cells to generate a virtual page and an encoding unit that generate an error correcting code for the virtual page and writes the data for three pages and the error correcting code in the non-volatile semiconductor memory.

Memory controller, semiconductor memory system, and memory control method

Devices, apparatuses, systems, and methods are disclosed for bit error reduction through varied data positioning. A write request module is configured to receive data for storage in an array of solid-state storage elements. The solid-state storage elements are accessible in parallel. A write module is configured to store the data in parallel to the array of solid-state storage elements with varied data positions for the data relative to different solid-state storage elements of the array. A read module is configured to read the data in parallel from the array of solid-state storage elements.

Bit error reduction through varied data positioning

Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells.

Joint encoding of logical pages in multi-page memory architecture

A multi-dimensional recording (MDR) system may include a group based coding circuit (GBCC) which can implement error correcting codes via outer codes. The GBCC can implement outer codes, including interleaving outer codes, in MDR systems where inner codewords include multiple memory groupings. The multiple memory groupings may be across different structural divisions within a data storage medium; or could be across multiple different data storage mediums.

Group based codes for multi-dimensional recording (MDR)

A method for re-using a soft decoder involves receiving soft data and hard data from memory cells in a memory device, mapping the soft data to a first set of soft information, mapping the hard data to a second set of soft information, and using the soft decoder to decode both the first set and second set of soft information.

Using a soft decoder with hard data

The minimum pseudocodeword weight w min of a linear graph-based code is more influential in determining decoding performance when decoded via iterative and linear programming decoding algorithms than the classical minimum distance d min under standard maximum-likelihood decoding Moreover, unlike the minimum distance which is unique to the code regardless of representation, the set of pseudocodewords, and therefore also the minimum pseudocodeword weight, depends on the graph representation used in decoding as well as on the communication channel. This means that a judicious choice of parity-check matrix is crucial for realizing the best potential of any graph-based code. In this paper, we introduce the notion of pseudoweight redundancy for the memoryless binary symmetric channel (BSC). Analogous to the stopping redundancy in the literature, this parameter gives the smallest number of rows needed for a parity-check matrix to have d min = w min. We provide some upper bounds on the BSC-pseudoweight redundancy and illustrate the concept with some results for Hamming codes, tree-based and finite geometry LDPC codes, Reed-Muller codes and Hadamard codes.

/pdf/on-the-pseudocodeword-weight-and-parity-check-matrix-3iz8regeex.pdf

On the pseudocodeword weight and parity-check matrix redundancy of linear codes

A storage device is configured to utilize different encoding and decoding schemes in reading and writing data to different regions of a storage device based on the position of the storage regions and/or component-specific physical characteristics of the regions. Each encoding scheme may include multiple different types of encoders selected based an optimization process for each region.

Storage device with multiple coding redundancies

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