David L. Rude
IBM
12 Papers
140 Citations
David L. Rude is an academic researcher from IBM. The author has contributed to research in topics: Error detection and correction & Chip. The author has an hindex of 6, co-authored 12 publications.
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Papers
A 5.2GHz microprocessor chip for the IBM zEnterprise™ system
James D. Warnock,Yuen H. Chan,William V. Huott,S. Carey,Michael Fee,Huajun Wen,M. J. Saccamango,Frank Malgioglio,Patrick J. Meaney,Donald W. Plass,Y.-H. Chan,M. Mayo,Guenter Mayer,L. Sigal,David L. Rude,R. Averill,Michael H. Wood,Thomas Strach,Howard H. Smith,Brian W. Curran,Eric M. Schwarz,Lee Evan Eisen,D. Malone,S. Weitzel,Pak-Kin Mak,T. J. McPherson,Charles F. Webb +26 more
- 07 Apr 2011
TL;DR: The microprocessor chip for the IBM zEnterprise 196 (z 196) system is a high-frequency, high-performance design that adds support for out-of-order instruction execution and increases operating frequency by almost 20% compared to the previous 65nm design, while still fitting within the same power envelope.
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Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System
James D. Warnock,Yiu-Hing Chan,S. Carey,Huajun Wen,Patrick J. Meaney,G. Gerwig,Howard H. Smith,Yuen Chan,John Davis,Paul A. Bunce,Antonio R. Pelella,Daniel Rodko,Pradip Patel,Thomas Strach,D. Malone,Frank Malgioglio,Jose L. Neves,David L. Rude,William V. Huott +18 more
TL;DR: The core and chip design methodology and specific design features are presented, focusing on techniques used to enable high-frequency operation, including chip power, IR drop, and supply noise are discussed, being key design focus areas.
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Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module
James D. Warnock,Yuen Chan,Hubert Harrer,S. Carey,Gerard M. Salem,Doug Malone,Ruchir Puri,Jeffrey A. Zitz,Adam R. Jatkowski,Gerald Strevig,Ayan Datta,Anne E. Gattiker,Aditya Bansal,Guenter Mayer,Yiu-Hing Chan,M. Mayo,David L. Rude,L. Sigal,Thomas Strach,Howard H. Smith,Huajun Wen,Pak-Kin Mak,C-L Kevin Shum,Donald W. Plass,Charles F. Webb +24 more
TL;DR: Various aspects of the design are explored in detail, with most of the focus on the CP chip, including the circuit design implementation, clocking, thermal modeling, reliability, frequency tuning, and comparison to the previous design in 45nm technology.
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5.5GHz system z microprocessor and multi-chip module
James D. Warnock,Y.-H. Chan,Hubert Harrer,David L. Rude,Ruchir Puri,S. Carey,Gerard M. Salem,Guenter Mayer,Yiu-Hing Chan,M. Mayo,Adam R. Jatkowski,Gerald Strevig,L. Sigal,Ayan Datta,Anne E. Gattiker,Aditya Bansal,D. Malone,Thomas Strach,Huajun Wen,Pak-Kin Mak,Chung-Lung Shum,Donald W. Plass,Charles F. Webb +22 more
- 28 Mar 2013
TL;DR: The new System z microprocessor chip (“CP chip”) features a high-frequency processor core running at 5.5GHz in a 32nm high-κ CMOS technology, a successor to the 45nm product, with significant improvements made to the core and nest.
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Patent
Semi-Flattened Pin Optimization Process for Hierarchical Physical Designs
Christopher J. Berry,Christopher M. Carney,David L. Rude,Eddy St. Juste +3 more
- 13 Sep 2006
TL;DR: In this paper, a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of which comprised of leaf cells, accessed via an input terminal and an output terminal, is presented.
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