A trench capacitor with a buried plate is formed with a single etching process by the expedient of filling the trench so formed and lined with diffusion source material with resist by baking and reflowing the resist which also serves to adjust exposure sensitivity of the resist such that exposure and development of the resist removes the resist to a repeatable and uniform depth. Remaining resist allows etching of the diffusion source layer to a very accurate dimension. Thus only a readily formed oxide or TECS layer is needed to confine impurities during diffusion to form the buried plate. An isolation collar can be formed after recess of the fill to avoid formation of step corners and erosion of the isolation collar by repeated fill and etch back processes while permitting maximum capacitance to be achieved for a given trench "footprint".

Method of making single-step trenches using resist fill and recess

Methods and compositions for the selective etching of silicon in the presence of p-doped silicon are disclosed whereby a portion of a silicon surface may be dissolved while a p-doped pattern in the surface remains substantially undissolved. The compositions comprise (a) an aqueous solution of an alkali metal hydroxide or a tetraalkylammonium hydroxide; and (b) a high flash point alcohol, phenol, polymeric alcohol, or polymeric phenol.

Methods and compositions for the selective etching of silicon

The preferred embodiments of the present invention overcome the limitations of the prior art by providing a method for forming the source/drain diffusions in a vertical transistor structure that results in improved channel length uniformity. In one embodiment, the present invention is used to form source/drain and bitline diffusion structures for use in pillar memory cells. Additionally, in another embodiment, the present invention is used to form source/drain and plate diffusion structures in pillar memory cells. Both preferred embodiments deposit conformal photoresist on a pillar structure and use an off-axis exposure process to recess a dopant source layer to the proper depth along the pillar. The recessed dopant source layer can then be used to form the source/drain/bitlines diffusions or source/drain/plate diffusions in the pillar memory device.

Method for forming pillar memory cells and device formed thereby

A method of forming a coupled capacitor and transistor is provided. A trench is formed in a semiconductor substrate and an impurity-doped first conductive region is then formed by filling the trench with an impurity-doped first conductive material. The impurity-doped first conductive region is etched back to a first level within the trench. An insulating layer is then formed on a sidewall of the portion of the trench opened by the etching back of the impurity-doped first conductive region and a second conductive region is formed by filling the remainder of the trench with a second conductive material. The insulating layer and the second conductive region are etched back to a second level within the trench and an amorphous silicon layer is formed in the portion of the trench opened by the etching back of the insulating layer and the second conductive region. The undoped amorphous silicon layer is etched back to a third a level within the trench. The undoped amorphous silicon layer is then recrystallized. Impurities are outdiffused from the impurity-doped first conductive region to the semiconductor substrate through the recrystallized silicon layer. A source/drain region of the transistor is formed adjacent to an intersection of the trench and the surface of the semiconductor substrate. The outdiffused impurities and the recrystallized silicon layer constitute a buried strap for electrically connecting the first and second conductive layers in the trench to the source/drain region.

Controlled recrystallization of buried strap in a semiconductor memory device

A memory cell having a low storage node resistance and a method of manufacturing the same are provided. A trench type memory cell, in addition to storage node polysilicon, has other conductive material embedded in the storage node. Conductive material may be one of WSi, TiSi, W, Ti, and TiN. The additional conductive material provides a low storage node resistance which facilitates the realization of 256 Mbit memory cells and beyond.

Low resistant trench fill for a semiconductor device

The invention provides a method for electrically connecting a polysilicon-filled trench to a diffusion region in a semiconductor device, wherein the trench and diffusion region are separated by a dielectric. The method provides for formation of a strap or bridge contact by utilizing a diffusion barrier layer which prevents diffusion into an overlying polysilicon layer when a subsequent boron out-diffusion step is performed. Selective etching is then utilized to remove the polysilicon layer where no boron has diffused, leaving a polysilicon strap connecting the trench and diffusion region.

Boron out-diffused surface strap process

A semiconductor trench capacitor structure having a first level aligned insulation structure and buried strap that extends from within the trench into the semiconductor substrate. The semiconductor trench capacitor structure may be fabricated by forming a shallow trench extending into both the trench capacitor and the semiconductor substrate, depositing and densifying an insulating material within the shallow trench and using a resist layer to define and etch a strap trench aligned with the wall of the shallow trench, depositing a layer of conductive material within the strap trench and followed by depositing an insulating material therein.

Method of making semiconductor trench capacitor cell having a buried strap

Semiconductor trench capacitor cell having a buried strap

The invention provides a method for electrically connecting a polysilicon-filled trench (12) to a diffusion region (10) in a semiconductor device, wherein the trench (12) and diffusion region (10) are separated by a dielectric (14). The method provides for formation of a strap or bridge contact by utilizing a diffusion barrier layer (18) which prevents diffusion into an overlying polysilicon layer (32) when a subsequent boron (16) out-diffusion step is performed. Selective etching is then utilized to remove the polysilicon layer (32) where no boron has diffused, leaving a polysilicon strap connecting the trench and diffusion region.

Method of conducting strap formation in a semiconductor device

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Boron out-diffused surface strap process

Method of making semiconductor trench capacitor cell having a buried strap

Semiconductor trench capacitor cell having a buried strap

Method of conducting strap formation in a semiconductor device