The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.

· Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
· Views of FPGA programming beyond Verilog/VHDL
· Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes a novel reconfigurable fabric architecture, PipeRench, optimized to accelerate these types of computations. PipeRench enables fast, robust compilers, supports forward compatibility, and virtualizes configurations, thus removing the fixed size constraint present in other fabrics. For the first time we explore how the bit-width of processing elements affects performance and show how the PipeRench architecture has been optimized to balance the needs of the compiler against the realities of silicon. Finally, we demonstrate extreme performance speedup on certain computing kernels (up to 190x versus a modern RISC processor), and analyze how this acceleration translates to application speedup.

/pdf/piperench-a-co-processor-for-streaming-multimedia-2zu0mowwqv.pdf

PipeRench: a co/processor for streaming multimedia acceleration

PHiPAC was an early attempt to improve software performance by searching in a large design space of possible implementations to find the best one. At the time, in the early 1990s, the most efficient numerical linear algebra libraries were carefully hand tuned for specific microarchitectures and compilers, and were often written in assembly language. This allowed very precise tuning of an algorithm to the specifics of a current platform, and provided great opportunity for high efficiency. The prevailing thought at the time was that such an approach was necessary to produce near-peak performance. On the other hand, this approach was brittle, and required great human effort to try each code variant, and so only a tiny subset of the possible code design points could be explored. Worse, given the combined complexities of the compiler and microarchitecture, it was difficult to predict which code variants would be worth the implementation effort. PHiPAC circumvented this effort by using code generators that could easily generate a vast assortment of very different points within a design space, and even across very different design spaces altogether. By following a set of carefully crafted coding guidelines, the generated code was reasonably efficient for any point in the design space. To search the design space, PHiPAC took a rather naive but effective approach. Due to the human-designed and deterministic nature of computing systems, one might reasonably think that smart modeling of the microprocessor and compiler would be sufficient to predict, without performing any timing, the optimal point for a given algorithm. But the combination of an optimizing compiler and a dynamically scheduled mi-

Optimizing matrix multiply using PHiPAC: a portable, high-performance, ANSI C coding methodology

Form of Control Expression % Abstract Form of Control Expression % others 32.4 ! function-call 3.8 object 15.5 object < integer-constant 2.2 object == object 8.9 object > integer-constant 1.8 ! object 7.4 function-call == object 1.6 function-call 7.4 object > object 1.4 expression 5.7 object != integer-constant 1.3 object != object 4.2 function-call == integer-constant 1.2 object == integer-constant 4.0 object < object 1.1 January 30, 2008 v 1.1 15 6.8.4 Selection statements 1740 selection-statements Fu nc tio n de fin iti on s 1 10 100 1,000 10,000 0 25 50 75 100 × × if • • else switch × × ××××××××××××××××××××××××××××××× ×××××× × ××× × ××××× ×× ×××× × ×× × × × × × × ××× × × ××× ×× × ××× × × × ××× × ×

The New C Standard (Excerpted material) An Economic and Cultural Commentary

Long training times for high-accuracy deep neural networks (DNNs) impede research into new DNN architectures and slow the development of high-accuracy DNNs. In this paper we present FireCaffe, which successfully scales deep neural network training across a cluster of GPUs. We also present a number of best practices to aid in comparing advancements in methods for scaling and accelerating the training of deep neural networks. The speed and scalability of distributed algorithms is almost always limited by the overhead of communicating between servers, DNN training is not an exception to this rule. Therefore, the key consideration here is to reduce communication overhead wherever possible, while not degrading the accuracy of the DNN models that we train. Our approach has three key pillars. First, we select network hardware that achieves high bandwidth between GPU servers – Infiniband or Cray interconnects are ideal for this. Second, we consider a number of communication algorithms, and we find that reduction trees are more efficient and scalable than the traditional parameter server approach. Third, we optionally increase the batch size to reduce the total quantity of communication during DNN training, and we identify hyperparameters that allow us to reproduce the small-batch accuracy while training with large batch sizes. When training GoogLeNet and Network-in-Network on ImageNet, we achieve a 47x and 39x speedup, respectively, when training on a cluster of 128 GPUs.

/pdf/firecaffe-near-linear-acceleration-of-deep-neural-network-3c3ryai6qc.pdf

FireCaffe: Near-Linear Acceleration of Deep Neural Network Training on Compute Clusters

The Spert-II fixed point vector microprocessor system performs training and recall faster than commercial workstations for neural networks used in speech recognition research. We have packaged a prototype full custom vector microprocessor, TO, as the Spert-II (Synthetic Perceptron Testbed II) workstation accelerator system. We originally developed Spert-II to accelerate multiparameter neural network training for speech recognition research. Our speech research algorithms constantly change. Also, neural nets are often integrated with other tasks to form complete applications. We thus desired a general purpose, easily programmable accelerator that could speed up a range of tasks.

/pdf/spert-ii-a-vector-microprocessor-system-2ydsjja8ok.pdf

Spert-II: a vector microprocessor system

This manual contains the specification of the Torrent Instruction Set Architecture (ISA). Torrent is a vector ISA designed for digital signal processing applications. Torrent is based on the 32-bit MIPS-II ISA, and this manual is intended to be read as a supplement to the book "MIPS RISC Architecture" by Kane and Heinrich. Torrent is the ISA of the T0 vector microprocessor which is described in the separate "T0 Engineering Data" technical report.

Torrent Architecture Manual

We report on the development of a high-performance system for neural network and other signal processing applications. We have designed and implemented a vector microprocessor and packaged it as an attached processor for a conventional workstation. We present performance comparisons with workstations on neural network backpropagation training. The SPERT-II system demonstrates roughly 15 times the performance of a mid-range workstation and five times the performance of a high-end workstation with extensive hand-optimization of both workstation versions.

https://papers.nips.cc/paper/1067-spert-ii-a-vector-microprocessor-system-and-its-application-to-large-problems-in-backpropagation-training.pdf

SPERT-II: a vector microprocessor system and its application to large problems in backpropagation training

We report on our development of a high-performance system for neural network and other signal processing applications. We have designed and implemented a vector microprocessor and packaged it as an attached processor for a conventional workstation. We present performance comparisons with commercial workstations on neural network backpropagation training. The SPERT-II system demonstrates significant speedups over extensively hand-optimization code running on the workstations.

/pdf/spert-ii-a-vector-microprocessor-system-and-its-application-2ciyfxg43k.pdf

SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training

Spert-II: A Vector Microprocessor

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