Bridging cultures that have often been distant, Julia combines expertise from the diverse fields of computer science and computational science to create a new approach to numerical computing. Julia is designed to be easy and fast. Julia questions notions generally held as "laws of nature" by practitioners of numerical computing: 
1. High-level dynamic programs have to be slow. 
2. One must prototype in one language and then rewrite in another language for speed or deployment, and 
3. There are parts of a system for the programmer, and other parts best left untouched as they are built by the experts. 
We introduce the Julia programming language and its design --- a dance between specialization and abstraction. Specialization allows for custom treatment. Multiple dispatch, a technique from computer science, picks the right algorithm for the right circumstance. Abstraction, what good computation is really about, recognizes what remains the same after differences are stripped away. Abstractions in mathematics are captured as code through another technique from computer science, generic programming. 
Julia shows that one can have machine performance without sacrificing human convenience.

Julia: A Fresh Approach to Numerical Computing

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this paper, we present a test vector simulation-based approach for multiple design error diagnosis and correction. Diagnosis is performed through an implicit enumeration of the erroneous lines in an effort to avoid the exponential explosion of the error space as the number of errors increases. Resynthesis during correction is as little as possible so that most of the engineering effort invested in the design is preserved. Since both steps are based on test vector simulation, the proposed approach is applicable to circuits with no global binary decision diagram representation. Experiments on ISCAS'85 benchmark circuits exhibit the robustness and error resolution of the proposed methodology. Experiments also indicate that test vector simulation is indeed an attractive technique for multiple design error diagnosis and correction in digital VLSI circuits.

/pdf/design-error-diagnosis-and-correction-via-test-vector-2c6uhd17xo.pdf

Design error diagnosis and correction via test vector simulation

In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of current generation processors and the necessity for manual designer intervention throughout the design process, proving design correctness is a major concern. In this paper we discuss Verity, a formal verification program for symbolically proving the equivalence between a high-level design specification and a MOS transistor-level implementation. Verity applies efficient logic comparison techniques which implicitly exercise the behavior for all possible input patterns. For a given register-transfer level (RTL) system model, which is commonly used in present-day methodologies, Verity validates the transistor implementation with respect to functional simulation and verification performed at the RTL level. ∗Copyright c ©1994 International Business Corporation This document has been published in the IBM Journal on Research and Development, January 1995.

Verity—a formal verification program for custom CMOS circuits

This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional specification. The method efficiently propagates mismatched patterns from erroneous outputs backward into the network and calculates circuit regions which most likely contain the error(s). In contrast to previous approaches, the described technique does not depend on a fixed set of error models. Therefore, it is more general and especially suitable for transistor-level circuits, which have a broader variety of possible design errors than gate-level implementations. Furthermore, the proposed method is also applicable for incomplete sets of mismatched patterns and hence can be used not only as a debugging aid for formal verification techniques but also for simulation based approaches. Experiments with industrial CMOS circuits show that for most design errors the identified problem region is less than 3% of the overall circuit.

/pdf/error-diagnosis-for-transistor-level-verification-4ipazf0nu3.pdf

Error Diagnosis for Transistor-Level Verification

Traditionally, the circuit partitioning problem is done by first modeling a circuit as a graph and then partitioning is performed on the modeling graph. Using the concept of alternative wires, we propose an efficient method that is able to preserve a local optimal solution in the graph domain while a different graph, representing the same circuit, is generated. When a conventional graph partitioning technique reaches a local optimal solution, our proposed technique generates a different graph that is logically equivalent to the original circuit, and that has equal or better partitioning solution. Faced with a different graph which is newly generated, together with a currently good partitioning solution, a conventional graph partitioning technique may then escape from the local optimum and continue searching for better solutions in a different graph domain. The proposed technique can be combined with almost any graph partitioner. Experiments show encouraging results.

Circuit partitioning with logic perturbation

: Star-P is an interactive parallel scientific computing environment. It aims to make parallel programming more accessible. Star-P borrows ideas from Matlab-P, but is a new development. Currently only a Matlab interface for Star-P is available, but STAR-P is not limited to being a parallel Matlab. It combines all four parallel Matlab approaches in one environment, as described in the parallel Matlab survey: embarrassingly parallel, message passing, backend support and compilation. It also integrates several parallel numerical libraries into one single easy-to-use piece of software. The focus of Star-P is to improve user productivity in parallel programming. We believe that Star-P can dramatically reduce the difficulty of programming parallel computers by reducing the time needed for development and debugging. To achieve productivity, it is important that the user interface is intuitive to the user. For example, a large class of scientific users are already familiar with the Matlab language. So it is beneficial to use Matlab as a parallel programming language. Additions to the language are minimal in keeping with the philosophy to avoid re-learning. Also, as a design goal, our system does not distinguish between serial data and parallel data.

/pdf/star-p-high-productivity-parallel-computing-541krjgdqv.pdf

Star-P: High Productivity Parallel Computing

Three-dimensional shape construction and recognition by fusing intensity and structured lighting

Redundancy removal is an important step in combinational logic optimisation. After a redundant wire is removed, other originally redundant wires may become irredundant, and some originally irredundant wires may become redundant. When multiple redundancies exist in a circuit, this creates a problem where we need to decide which redundancy to remove first. The authors present both a theoretical analysis and a very efficient heuristic to deal with multiple redundancies. Each redundant wire is associated with a Boolean function that describes how the wire can remain redundant after removing other wires. When multiple redundancies exist, this set of Boolean functions characterises the global relationship among redundancies. The proposed heuristic for dealing with the multiple-redundancy problem is very efficient and the experimental results are very promising.

Removing multiple redundancies in combinational circuits

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