Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates

The fabrication of electrical interconnects to provide power for and communication with computers as their component complementary metal oxide semiconductor (CMOS) devices continue to shrink in size presents significant materials and processing compatibility challenges. We describe here our efforts to address these challenges using top-surface imaging and hybrid photoresist/self-assembled monolayer patterning approaches, in conjunction with selective electroless metal deposition, to develop processes capable of fabricating appropriate submicron and nanoscale metal features useful as electrical interconnects, as well as plasma-etch-resistant masks and metal diffusion barriers. Our efforts focus on the development of cost-effective methods compatible with a manufacturing environment that satisfy materials and process constraints associated with CMOS device production. We demonstrate the fabrication of approximately 50-nm-width features in metal with high fidelity and sufficient control of edge acuity to satisfy current industry design rules using our processes and discuss the challenges and opportunities for fabrication of analogous sub-10-nm metal features.

Selective Electroless Metallization of Patterned Polymeric Films for Lithography Applications

An overview of the channelization function, the parallel signal processing techniques used in channelizers, the signal processing functions, and the critical channelizer parameters is given. Signal processing capabilities that use analog techniques suitable for channelized receivers are compared with those capabilities that can be obtained by using current or foreseen digital techniques. The receiver signal-processing needs are outlined, and the limitations of digital signal processing in terms of the overall receiver signal processing needs are discussed. Options and tradeoffs at the receiver and channelizer technology levels are discussed. Promising channelizer technologies, including components, that have been or potentially may be implemented with small volumes and moderate dynamic range are described. Parallel signal-processing methods, architectural techniques, and hardware for channelized receiver technologies that can be implemented in a small volume (tens of channels per in/sup 3/) with a moderately high dynamic range (>50 dB) are discussed. These include the surface-acoustic-wave (SAW), bulk-acoustic-wave (BAW), magnetostatic-wave (MSW), and acoustooptical (AO) channelizer technologies. The critical signal preprocessing functions required in channelized receivers before the needed information is passed on to the host computer, so that the host computer can be operated at a possible computation rate, are discussed, and the first successful monolithic integrated circuit preprocessor component for channelizers, is presented. >

Advanced channelization for RF, microwave, and millimeterwave applications

Polycrystalline silicon‐gate metal‐oxide‐semiconductor (MOS) capacitors have been fabricated with high‐temperature anneals from 800 to 950 °C after gate oxidation and polycrystalline silicon deposition. Temperatures from 800 to 875 °C are found to have very little effect on the radiation response of these devices. However, a rapid increase in radiation‐induced oxide‐trapped charge, ΔVot, is observed for anneal temperatures above 875 °C. This increase in ΔVot coincides with an experimentally observed change in the polycrystalline silicon grain structure. The anneal temperature was found to have a much smaller effect on radiation‐induced interface‐trap charge. The correlation of these results to other properties, e.g., stress, is discussed.

Effect of post-oxidation anneal temperature on radiation-induced charge trapping in metal-oxide-semiconductor devices

The acid-diffusion effect on line edge roughness (LER) in a negative-type chemically amplified resist of electron beam lithography was evaluated experimentally. The edge roughness evaluation method was utilized to quantify the acid-diffusion length. Adjusting the prebaking temperature controlled the acid-diffusion coefficient in the range from 8.1 nm2/s at 70 °C to 0.8 nm2/s at 130 °C. Acid diffusion reduced the LER of a 100 nm isolated line from 6.9 to 4.0 nm while increasing the diffusion length from 15 to 44 nm, but a too-long diffusion length degraded line and space patterns. These results suggest that acid diffusion has two opposing effects on LER: one is the smoothing effect reducing LER and the other is the degrading image contrast effect increasing LER. It is concluded that LER occurs as a consequence of the amplification of the so-called uncertainty band by the slope of the quasibeam profile. The bandwidth signifies the effect of molecular structure, the spatial dispersion of photochemical events caused by shot noise, the smoothing effect of acid diffusion, and development uncertainty at the pattern edge. The magnitude of the amplification is determined by the slope of the quasibeam profile that comprises aerial-image quality, acid-diffusion length, and resist contrast.

Study of the acid-diffusion effect on line edge roughness using the edge roughness evaluation method

Mechanical and electrical properties were correlated in LPCVD SiNx;Si structures through the characterization of six wafers patterned with MNS capacitors whose insulator films were deposited rich in Si under various processing conditions. The samples were measured for mechanical stress at the SiSiNx interface with X-ray diffraction. The deposited SiNx films were measured for stoichiometry by Rutherford backscattering spectroscopy. Low-temperature C-V measurements were used for the first time to estimate SiSiNx interface trap densities in the capacitors. The interface trap densities were confirmed with the aid of a model based on a numerical analysis of the capacitor small-signal response. The measurement results indicate that an increase in the Si/N ratio in the insulating films was accompanied by a decrease in the film tensile stress. Those SiNx films made sufficiently rich in Si were successfully deposited under compressive stress. Furthermore, a decrease in the magnitude of the stress was accompanied by a decrease in interface trap densities, suggesting that interfacial mechanical stress may be influential in the formation of SiSiNx interface traps. Interface trap densities were lowest in those structures whose insulating films were deposited under compression.

The interaction of stoichiometry, mechanical stress, and interface trap density in LPCVD Si-rich SiNx;Si structures

Electroless Ni exhibits excellent plasma etch resistance and has been successfully employed as a hard etch mask in the fabrication of microelectronic and microelectromechanical components and templates for contact printing and biomedical applications. The use of a catalytic agent to initiate electroless deposition is known to directly affect the microstructure and properties of the deposited metal and thus the etch resistance and potential pattern resolution. We have previously reported the development of tin-free colloidal Pd(II) electroless catalysts, which are suitable for initiating the deposition of patterned EL Ni films for use as plasma etch masks. In this work we examine the effect of the Pd(II) precursor on feature resolution, Ni plating rate, and etch resistance. The etch selectivity of deposited films is determined by real-time endpoint detection using laser reflectometry. Both film morphology and the formation of nickel silicides were found to impact the etch resistance in thin (<20 nm) films....

Application of Electroless Nickel−Boron Films for High-Selectivity Pattern Transfer Processes

The work presents a unique investigation of the role of postexposure bake (PEB) on resist insolubility, PEB reaction kinetics, and the high resolution behavior of Microposit™ SAL-601. Patterns of 20–100 μm rectangles and single pass isolated lines were written on a JEOL JBX-5DII e-beam lithography system operated at 50 kV. The effects of PEB temperatures of 90–110 °C for periods of 1–11 min on resist insolubility and linewidth were examined. The samples were developed in MF-322 or acetone. The range of patterns allowed measurement of both the resist exposure curves and the line spread for each PEB condition. Insolubility in MF-322 can result from protection reactions and/or crosslinking reactions. Acetone insolubility, a characteristic of crosslinked resist, was observed at PEB temperatures of 100 °C and above. At 90 °C, acetone insolubility (crosslinking) was observed only after a PEB of 11 min. From the resist exposure curves for a sequence of PEB times, reaction orders for the PEB processes that led to...

Electron-beam nanolithography, acid diffusion, and chemical kinetics in SAL-601

A double‐crystal x‐ray topograph was used to determine local strain in metal‐oxide‐semiconductor (MOS) transistor test chips. The double‐crystal machine could sense strains as small as 10−6, with a spatial resolution of a few micrometers. Results indicate that two types of strain are present: local surface strain as well as the more familiar strain due to bulk deformation of the crystal. Both types of strain have been correlated with surface mobility changes in n‐channel metal‐oxide‐semiconductor (nMOS) transistors.

Double‐crystal x‐ray topographic determination of local strain in metal‐oxide‐semiconductor device structures

A novel method is reported for reducing the proximity effect in high‐resolution electron beam patterning of high atomic number materials such as tungsten. The method involves interposing a thin (50–400 nm) layer of SiO2 between the resist and the underlying high‐Z substrate. Examples are shown in which gratings of 0.2 μm lines with a 0.5 μm period were written without proximity effect compensation. Optimal intermediate layer thickness for the best resolution of the gratings is determined to be 200 nm. A Monte Carlo model of electron scattering including inelastic processes has been implemented to interpret our experimental results. The model presented shows that having the low atomic number SiO2 layer between the resist and the tungsten prevents the fast secondary electrons being generated at the surface of the tungsten from propagating back into the resist, suggesting a mechanism for proximity effect reduction. The results presented here have important practical applications for x‐ray mask making.

Proximity effect reduction in x‐ray mask making using thin silicon dioxide layers

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

David I. Ma

Author Tools

Chat about Author