Daniel Rodko
IBM
16 Papers
111 Citations
Daniel Rodko is an academic researcher from IBM. The author has contributed to research in topics: Static random-access memory & Chip. The author has an hindex of 7, co-authored 16 publications.
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Papers
6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM
Rajiv V. Joshi,Robert M. Houle,Kevin A. Batson,Daniel Rodko,Pradip Patel,William V. Huott,R.L. Franch,Y.H. Chan,Donald W. Plass,S. Wilson,P. Wang +10 more
- 14 Jun 2007
TL;DR: A fully functional read and half select disturb-free 1.2 Mb SRAM is demonstrated at 1.6+ GHz at IV, 25degC and yield of 90-100%.
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Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System
James D. Warnock,Yiu-Hing Chan,S. Carey,Huajun Wen,Patrick J. Meaney,G. Gerwig,Howard H. Smith,Yuen Chan,John Davis,Paul A. Bunce,Antonio R. Pelella,Daniel Rodko,Pradip Patel,Thomas Strach,D. Malone,Frank Malgioglio,Jose L. Neves,David L. Rude,William V. Huott +18 more
TL;DR: The core and chip design methodology and specific design features are presented, focusing on techniques used to enable high-frequency operation, including chip power, IR drop, and supply noise are discussed, being key design focus areas.
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Patent
Array self repair using built-in self test techniques
William V. Huott,Franco Motika,Pradip Patel,Daniel Rodko +3 more
- 31 Jan 2005
TL;DR: In this paper, a soft-fuse test algorithm is distributed on-chip from an ABIST engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad elements and repair those that are fixable.
18
A Low Power and High Performance SOI SRAM Circuit Design with Improved Cell Stability
Rajiv V. Joshi,Y.-H. Chan,Donald W. Plass,Timothy J. Charest,R. Freese,Rolf Sautter,William V. Huott,Uma Srinivasan,Daniel Rodko,Pradip Patel,Philip George Shephard,Tobias Werner +11 more
- 01 Oct 2006
TL;DR: An embedded CMOS static random access memory (SRAM) including the array and a method of accessing cells in the array with improved cell stability for scalability and performance (over 5 GHz) is demonstrated in hardware using 65 nm Partially Depleted Silicon on Insulator (PD SOI) technology.
13
A high performance 2.4 Mb L1 and L2 cache compatible 45nm SRAM with yield improvement capabilities
Rajiv V. Joshi,Robert M. Houle,Daniel Rodko,Pradip Patel,William V. Huott,R.L. Franch,Y.-H. Chan,Donald W. Plass,S. Wilson,S. Wu,Rouwaida Kanj +10 more
- 18 Jun 2008
TL;DR: A hardware based, fully functional, stable 2.4 Mb L1 and L2 Cache compatible 6T embedded SRAM is demonstrated, supported by newly developed fast Monte Carlo technique useful for improved cell stability, writeability, and enhanced yield.
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