Daniel K. Weinlader
Synopsys
22 Papers
239 Citations
Daniel K. Weinlader is an academic researcher from Synopsys. The author has contributed to research in topics: Clock domain crossing & Backplane. The author has an hindex of 9, co-authored 22 publications.
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Papers
An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS
TL;DR: This paper describes a backplane transceiver, which uses pulse amplitude modulated four-level (PAM-4) signaling and continuously adaptive transmit-based equalization to move 2.5-GBd/s symbols totalling 5 Gb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors.
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A multigigabit backplane transceiver core in 0.13-/spl mu/m CMOS with a power-efficient equalization architecture
K. Krishna,David A. Yokoyama-Martin,A. Caffee,Clinton D. Jones,M. Loikkanen,J. Parker,R. Segelken,Jeffrey Lee Sonntag,John T. Stonick,S. Titus,Daniel K. Weinlader,Skye Wolfer +11 more
TL;DR: In this article, a binary backplane transceiver core in 013/spl mu/m dual-gate lowvoltage (LV) CMOS, operating at 06-96 Gb/s with an area of 056 mm/sup 2/, is presented.
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An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 /spl mu/m CMOS
Jeffrey L. Sonntag,John T. Stonick,James Gorecki,B. Beale,B. Check,Xue-Mei Gong,J. Guiliano,Kyong Lee,B. Lefferts,David O. Martin,Un-Ku Moon,A. Sengir,S. Titus,Gu-Yeon Wei,Daniel K. Weinlader,Yaohua Yang +15 more
- 07 Aug 2002
TL;DR: A novel backplane transceiver, which uses PAM-4 (pulse amplitude modulated four level) signalling and continuously adaptive transmit based equalization to move 5 Gcb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors is described.
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A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25/spl mu/m CMOS
Gu-Yeon Wei,John T. Stonick,Daniel K. Weinlader,Jeffrey Lee Sonntag,S. Searles +4 more
- 09 Feb 2003
TL;DR: In this paper, the authors describe the implementation of a 500MHz clock synthesizer that operates either as a multiplying phase-locked loop (MPLL) or a multiplying delay-locked loops (MDLL) with a 2.5V supply.
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A 15mW 3.125GHz PLL for serial backplane transceivers in 0.13 /spl mu/m CMOS
J. Parker,Daniel K. Weinlader,Jeffrey Lee Sonntag +2 more
- 29 Aug 2005
TL;DR: In this article, a 3.125GHz PLL was fabricated in a 0.13 /spl mu/m CMOS process in an area of 0.064mm/sup 2/
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