Daniel Barcelos
Universidade Federal do Rio Grande do Sul
9 Papers
79 Citations
Daniel Barcelos is an academic researcher from Universidade Federal do Rio Grande do Sul. The author has contributed to research in topics: Shared memory & Cache-only memory architecture. The author has an hindex of 6, co-authored 9 publications.
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Papers
Impact of task migration in NoC-based MPSoCs for soft real-time applications
Eduardo Wenzel Brião,Daniel Barcelos,Fabio Wronski,Flávio Rech Wagner +3 more
- 12 Dec 2007
TL;DR: Experimental results show that, even with a higher overhead than other possible approaches, task migration may be applied in NoC-based architectures, since it pays off the costs involved in the transfer in terms of overall system performance and energy consumption and may help to improve the fulfillment of task deadlines in soft real-time systems.
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A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs
Daniel Barcelos,Eduardo Wenzel Brião,Flávio Rech Wagner +2 more
- 03 Sep 2007
TL;DR: Results are very encouraging and indicate that the proposed hybrid organization reduces the code transfer energy by 24% and 10% on average, as compared to global- and distributed-only memory organizations, respectively.
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A virtual platform for multiprocessor real-time embedded systems
Elias T. Silva,Daniel Barcelos,Flávio Rech Wagner,Carlos Eduardo Pereira +3 more
- 24 Sep 2008
TL;DR: This paper presents a virtual platform for the development and test of application software, low-level software, and hardware components for an MPSoC (Multiprocessor System- on-Chip) platform, where components are interconnected by a network-on-chip (NoC).
Performance and Energy Evaluation of Memory Organizations in NoC-Based MPSoCs under Latency and Task Migration
Gustavo Girao,Daniel Barcelos,Flávio Rech Wagner +2 more
- 12 Oct 2009
TL;DR: This chapter presents a study on the performance and energy consumption arising from distinct memory organizations in an NoC-based MPSoC environment and results suggest that shared and distributed shared memories present the best results for applications with high data transferring needs.
A differential low power wake-up circuit based on systematic offset for BAP UHF RFID tag
TL;DR: The wake-up circuit was designed and implemented in standard CMOS 0.18 µm process as part of an UHF RFID battery-assisted passive system, achieving a sensitivity of − 31 dBm and consuming only 150 nA.
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