A brand new 3D integrated circuit (3DIC) solution, System on Integrated Chips (SoIC^™), has been successfully developed to integrate active and passive chips into a new integrated SoC system to meet ever-increasing market demands on higher computing efficiency, wilder data bandwidth, higher functionality packaging density, lower communication latency, and lower energy consumption per bit data. 3D packaging is challenging and requires overcoming three major challenges - thermal, power delivery, and yield. The SoIC, as industry-first 3D logic-on-logic and memory-on-logic chiplet stacking technology platform, enables the heterogeneous integration (HI) of known good dies (KGDs) with different chip sizes, functionalities and wafer node technologies, all to be integrated in a single, compact new system chip. From external appearance, SoIC looks like a general SoC chip with multiple pre-designed heterogeneous functional chips embedded. As SoIC is fabricated using "front-end" process, it can be holistically integrated into variant "back-end" advanced packaging technology platforms such as flip chip, integrated fan-out (aka InFO), 3DIC, and 2.5D with Si interposer (e.g. CoWoS^™) [1-2] to provide a miniaturized and highly integrated HI SiP for the future HPC, AI, 5G, and edge computing applications. With the innovative bonding scheme, SoIC enables the strong bonding pitch scalability for chip I/O to realize a high density die-to-die interconnects. The bond pitch starts from sub-10 μm rule. Short die-to-die connection of SoIC has the merits of smaller form-factor, higher bandwidth, better power integrity (PI), signal integrity (SI), and lower power consumption comparing to the current industry state-of-the-art packaging solutions. In this paper, we demonstrated for the first time an integration of SoIC chip into InFO_PoP without increasing its form-factor. The SoIC was made on a logic-on-logic stacking to validate the design rules, process maturity, and reliability.

System on Integrated Chips (SoIC(TM) for 3D Heterogeneous Integration

This paper describes the features and performance of an analog and RF device technology development on a 14-nm logic FinFET platform. An optimized single-side gate contact RF device layout shows a ${F}_{t}/{F}_{\text {max}}$ of 314/180 GHz and 285/140 GHz for ${N}$ and PFinFET device, respectively. The double-side gate contact structure with contact on either end of active gate enhances the peak ${F}_{\text {max}}$ performance to 227 and 195 GHz for both ${N}$ and PFinFET devices, respectively. A significant boost in the PFinFET RF performance is observed compared to 28-nm planar PFET, which is attributed to the source/drain SiGe epitaxy stressor that results in higher hole carrier mobility. On the other hand, the thin channel body of FinFET structure facilitates a better electrostatic control of gate over the channel region and hence suppresses short channel effects including the drain-induced barrier lowering. Consequently, a significantly higher self-gain ( ${G}_{m}/{G}_{\text {ds}})~40$ and 34 for both NFinFET and PFinFET is achieved. In addition, N/PFinFETs demonstrate superior 1/f noise of 17/35 fV $^{2}\mu \text{m}^{2}$ /Hz at 1 kHz compared to 171/106 fV $^{\mathrm {\mathbf {2}}}\mu \text{m}^{2}$ /Hz of 28-nm planar N/PFETs. To extend the low-voltage operation and power saving of FinFET RF platform, ultralow ${V}_{t}$ N/PFinFETs in the range of 50 mV ${V}_{t}\text{s}$ are also developed. Furthermore, a deep n-well process is added to the platform to provide device and circuit isolation from substrate and supply noise, while realizing the creation of new devices such as vertical NPN, PCAP, and high breakdown voltage deep n-well junction diodes. Overall, a superior ${F}_{t}/{F}_{\textsf {max}}$ , high self-gain, low 1/f noise, and robust substrate isolation characteristics extend the capability of this new 14-nm FinFET technology to the analog and RF circuit applications.

14-nm FinFET Technology for Analog and RF Applications

With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs) will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave) wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC) and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

For the first time, a novel drain-extended tunnel FET (DeTFET) device is disclosed in this paper, while addressing the need for high-voltage/high-power devices for system-on-chip and automotive applications in beyond FinFET technology nodes. Operation of the proposed DeTFET device is presented with physics of band-to-band tunneling and associated carrier injection. Device’s intrinsic (dc/switching), analog, and RF performance is compared with the state-of-the-art drain-extended nMOS (DeNMOS) device. The proposed device for 11 V breakdown voltage offers $15\times $ better subthreshold slope, $8\times $ lower off-state leakage, $2\times $ higher ON current, and absence of channel length modulation and drain induced barrier lowering, while keeping $2.5\times $ lower threshold voltage. This results into significantly better ON resistance for a range of gate voltages, higher transconductance, orders of magnitude higher intrinsic transistor gain, and better RF characteristics, when compared with the DeNMOS device. Finally, device design guidelines are presented and scalability, without affecting breakdown voltage, of the proposed device is compared with the DeNMOS device.

Drain Extended Tunnel FET—A Novel Power Transistor for RF and Switching Applications

The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology co-optimization, modest reduction in fin, gate, and interconnect pitch as well as process inn-ovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next foundry node. However, analog/mixed-signal circuits do not fully realize these improvements. They become more cumbersome to design, having worse parasitic resistance and capacitance, stronger layout-dependent effects, and layout growth in some situations. Furthermore, early adopters of these cutting-edge finFET nodes must cope with the complications of design concurrent with technology development for shorter product time-to-market. We provide an overview of the key process technology elements enabling 7 nm and beyond to address analog/mixed-signal design challenges. From this insight, we offer layout guidelines aimed to reduce design vulnerability to technology and model immaturity.

Analog/mixed-signal design challenges in 7-nm CMOS and beyond

Continuous process-level and system-level innovation has driven Moore's Law scaling for the last fifty years, and will continue to do so in the next decades. In the last two decades, there has been an acceleration of new materials and devices into semiconductor manufacturing, such as low-k, strained Si, high-k, and FinFET [1–4], in order to continue process and cost scaling. At the same time, ever increasing component integration on SoCs has further driven cost scaling, allowing the current mobile era to take shape [5]. In the next decade, the focus of SoC innovation will be on patterning and low-resistance materials on the process side, and multi-die package integration on the system side.

Challenges of analog and I/O scaling in 10nm SoC technology and beyond

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Challenges of analog and I/O scaling in 10nm SoC technology and beyond