There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The notion of Abstract State Machines (ASMs), defined in [20], captures in mathematically rigorous yet transparent form some fundamental operational intuitions of computing, and the notation is familiar from programming practice and mathematical standards. This allows the practitioner to work with ASMs without any further explanation, viewing them as `pseudocode over abstract data’ which comes with a well defined semantics supporting the intuitive understanding. We therefore suggest to skip this chapter and to come back to it only should the need be felt upon further reading.

/pdf/abstract-state-machines-frjucl1ms5.pdf

Abstract State Machines

We consider the problem of reasoning with linear temporal logic on truncated paths. A truncated path is a path that is finite, but not necessarily maximal. Truncated paths arise naturally in several areas, among which are incomplete verification methods (such as simulation or bounded model checking) and hardware resets. We present a formalism for reasoning about truncated paths, and analyze its characteristics.

/pdf/reasoning-with-temporal-logic-on-truncated-paths-3fdcfxc2ya.pdf

Reasoning with Temporal Logic on Truncated Paths

We present an overview of results developed mainly at Verimag, by the author and his colleagues, on a framework for component-based construction, characterized by the following: the behavior of atomic components is represented by transition systems; components are built from a set of atomic components by using "glue" operators; for each component, it is possible to separate its behavior from its structure, due to specific properties of glue operators. We show an instance of this framework, which combines two independent classes of glue operators, interaction models and priorities. The combination of interaction models and priorities is expressive enough to encompass heterogeneous interaction and execution. We show that separation between behavior and structure is instrumental for correctness-by-construction. Finally, we discuss new research problems related to a structure-dependent notion of expressiveness.

/pdf/a-framework-for-component-based-construction-4tqek10avu.pdf

A framework for component-based construction

SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In this paper, we present an approach to overcome this problem by defining the semantics of SystemC by a mapping from SystemC designs into the well-defined semantics of Uppaal timed automata. The informally defined behavior and the structure of SystemC designs are completely preserved in the generated Uppaal models. The resulting Uppaal models allow us to use the Uppaal model checker and the Uppaal tool suite, including simulation and visualization tools. The model checker can be used to verify important properties such as liveness, deadlock freedom or compliance with timing constraints. We have implemented the presented transformation, applied it to two examples and verified liveness, safety and timing properties by model checking, thus showing the applicability of our approach in practice.

/pdf/model-checking-systemc-designs-using-timed-automata-487yj986pr.pdf

Model checking SystemC designs using timed automata

The verification of digital designs, i.e., hardware or embedded hardware/software systems, is an important task in the design process. Often more than 70% of the development time is spent for locating and correcting errors in the design. Therefore, many techniques have been proposed to support the debugging process. Recently, simulation and test methods have been accompanied by formal methods such as equivalence checking and property checking. However their industrial applicability is currently restricted to small or medium sized designs or to a specific phase in the design cycle. In this paper, we present a method for verifying temporal properties of systems described in an executable description language. Our method allows the user to specify properties about the system in finite linear time temporal logic. These properties are translated to a special kind of finite state machines which are then efficiently checked on-the-fly during each simulation run. Properties may be placed anywhere in the system description and violations are immediately indicated to the designer.

/pdf/simulation-guided-property-checking-based-on-a-multi-valued-2sjwwqxjy0.pdf

Simulation-guided property checking based on a multi-valued AR-automata

Equivalence checking of two circuits is performed at several stages in the design cycle of hardware designs and various commercial equivalence checkers, mostly based on Boolean logic, are already in the market. Design Error Diagnosis and Correction (DEDC) methods come into play when equivalence checking has proven two circuits to be different. In many cases, DEDC methods can locate and correct design errors fully automatically. In this paper, we present an efficient symbolic method for automatic error correction of both combinational and synchronous sequential circuits. We first address the problem of rectifying combinational circuits and then show how the problem of rectifying sequential circuits can be reduced to a combinational problem without unrolling the combinational logic parts. In addition, we introduce several optimizations to our algorithm. All optimizations are safe, meaning that they neither affect the number of computed solutions nor do they neither affect the number of computed solutions nor do they decrease the quality of results. Our experimental results show that the discussed optimization strategies can make the rectification procedure 2 to 16 times faster than the unoptimized algorithm.

Efficient design error correction of digital circuits

The verification of systems, i.e., hardware or hardware/software systems, is an important task in the design process. More than 70% of the development time is spend for locating and correcting error in the design. Therefore, many techniques have been proposed to support the debugging process. Recently, simulation and test methods have been accompanied by formal methods such as equivalence checking and property checking. However, their industrial applicability is curl-entry restricted to small or medium sized designs of to a specific phase in the design cycle. In this paper, we present a method for verifying temporal properties of systems described in an executable description language. Our method allows the user to specify properties about the system in finite linear time temporal logic (FLTL). These properties are checked on-the-fly during each simulation run, and each violation is immediately indicated to the designer.

Checking temporal properties under simulation of executable system descriptions

Due to the increasing complexity of VLSI circuit designs, errors are likely to happen at all stages in the design cycle. Already today, more then 70% of the development time is spend on circuit debugging. This number is even expected to grow in future and imposes yet unsolved challenges on tomorrow's EDA industry. Therefore, the verification of systems (hardware or embedded hardware/software systems) is one of the most important tasks in the design process. To cope with the increasing complexity, various attempts have been made to increase productivity. Among those, one is to provide better suited system description languages (SDLs) supporting the designer at all levels of abstraction. Another important issue is the development of tailored validation and verification techniques. In the past, most verification techniques have been based on simulation and test methods. Recently, formal methods such as temporal property checking has become increasingly popular. However, their industrial applicability is currently restricted to small or medium sized design or to a specific phase in the design cycle. The author describe a simulation based method for verifying temporal properties of systems described in SystemC/sup TM/. The method allows the user to specify properties about the system in a finite version of linear time temporal logic (FLTL). These properties are then checked on-the-fly during each simulation run, and each violation is immediately signaled to the designer.

Simulation meets verification-checking temporal properties in SystemC

Boolean equivalence checking is a well established approach for verifying combinational circuits and is on the verge of becoming an integrated part of the design cycle. Previously (1999), we have presented a method for performing automatic error correction in combinational circuits if equivalence checking fails. However like all other automatic error correction techniques proposed in the past, it cannot handle circuits containing tri-states. This is a restriction for practical applications since tri-states occur in many real-life circuits. In this paper we present two solutions how the rectification method can be extended to locate and rectify errors in tri-state circuits. This makes the method applicable to a much broader range of circuits.

Automatic error correction of tri-state circuits

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

D.W. Hoffmann

Author Tools

Chat about Author