This paper describes a four-channel ADSL2+ analog front-end (AFE) targeted at a central office application, with a power consumption of 75 mW per channel. The design is implemented using a modern 0.13-/spl mu/m CMOS process. The AFE consists of a 14-bit ADC and DAC, a very low-noise high-linearity automatic gain control (AGC), analog filter blocks, and digital decimation and interpolation filter stages. The design has been optimized to achieve the lowest possible power consumption, high performance, and cost efficiency.

A four-channel ADSL2+ analog front-end for CO applications with 75 mW per channel, built in 0.13-/spl mu/m CMOS

An analog front-end IC with integrated line driver for an ADSL system is presented. The IC contains all analog functions including gain-controlled transmit- and receive-amplifiers, highly linear continuous-time low pass filters including on-chip automatic tuning, 14 bit ADC and DAC as well as a digitally controlled crystal oscillator. The IC has been fabricated in a mixed-signal 0.6 µm DPTM BiCMOS technology with a chip area of 29mm2and a power consumption of only 800mW, using 3.3V supply for all blocks except 12V supply for the line driver.

http://ieeexplore.ieee.org/iel5/9920/31529/01471347.pdf

An ADSL-RT full-rate analog frontend IC with integrated line driver

An analog front-end IC with integrated line driver for an ADSL system is presented. The IC contains all analog functions including gain-controlled transmit- and receive-amplifiers, highly linear continuous-time low pass filters including on-chip automatic tuning, 14 bit ADC and DAC as well as a digitally controlled crystal oscillator. The IC has been fabricated in a mixed-signal 0.6 /spl mu/m DPTM BiCMOS technology with a chip area of 29 mm/sup 2/ and a power consumption of only 800 mW, using 3.3 V supply for all blocks except 12 V supply for the line driver.

A 800 mW, full-rate ADSL-RT analog frontend IC with integrated line driver

A Butterworth 2
 nd
-order programmable filter for telecommunication applications is presented. In order to operate with signals in a programmable bandwidth, the block exhibits two cut-off frequencies (in the 2MHz-to-20MHz range). A programmable gain (in the -15dB-to-9dB range) is required in order to optimize the channel performances in terms of signal-to-noise ratio. Power reduction is achieved embedding the output stage in the filter and operating the filter with two supply-voltages for the input stage (1.5V) and for the output stage (3.3V). An input common-mode feedback circuit compensates the difference between the input and output commode mode voltages. The power consumption varies from 29mW to 38mW (when the filter dc gain is -15dB), because for dc gains lower than one the input CMFB circuit is needed and his contribution in terms of power consumption has to be considered. The filter is designed in a 0.13 mum CMOS technology, and performs a THD of -80dBc for a 3V
 pp,diff
 output signal with a load of 500Omega and 10pF in parallel. The maximum output referred noise is -142dBm for a 100Omega reference-load and a 9dB dc-gain

A Programmable Double Supply Filter&Drive Block for Telecommunication Applications

A 0.25µm 2.5V CMOS analog front-end IC for an ADSL system is presented. The IC contains all analog functions including gain-controlled transmit and receive amplifiers, highly linear continuous-time low pass filtering including on-chip automatic tuning, 8.8Ms/s ADC and DAC as well as a crystal driver and a DAC-controlled VCO. The IC has been realized in a mixed-signal 0.25µm triple-well CMOS technology, with a chip area of 25mm2, and a power consumption of only 300mW using 2.5V supply.

A low-voltage low-power 0.25&#181;m CMOS ADSL analog front-end IC

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A low-voltage low-power 0.25µm CMOS ADSL analog front-end IC

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A low-voltage low-power 0.25&#181;m CMOS ADSL analog front-end IC

A low-voltage low-power 0.25µm CMOS ADSL analog front-end IC