In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise problem, already a major issue in 2D, is even more severe in 3D. CMOS decoupling capacitors (decaps) have been used effectively for controlling power grid noise in the past, but with technology scaling, they have grown increasingly leaky. As an alternative, metal-insulator-metal (MIM) decaps, with high capacitance densities and low leakage current densities, have been proposed. In this paper, we explore the tradeoffs between using MIM decaps and traditional CMOS decaps, and propose a congestion-aware 3D power supply network optimization algorithm to optimize this tradeoff. The algorithm applies a sequence-of-linear-programs based method to find the optimum tradeoff between MIM and CMOS decaps. Experimental results show that power grid noise can be more effectively optimized after the introduction of MIM decaps, with lower leakage power and little increase in the routing congestion, as compared to a solution using CMOS decaps only.

/pdf/congestion-aware-power-grid-optimization-for-3d-circuits-4yx7lnyy9m.pdf

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

/pdf/congestion-aware-power-grid-optimization-for-3d-circuits-6didldir3j.pdf

Compared to their 2D counterparts, 3D integrated circuits provide the potential for tremendously increased levels of integration per unit footprint. While this property is attractive for many applications, it also creates more stringent design bottlenecks in the areas of thermal management and power delivery. First, due to increased integration, the amount of heat per unit footprint increases, resulting in the potential for higher on-chip temperatures. The task of thermal management must necessarily be shared both by the heat sink, which transfers internally generated heat to the ambient, and by using thermally conscious design methods. Second, the power to be delivered to a 3D chip, per package pin, is tremendously increased, leading to significant complications in the task of reliable power delivery. This chapter presents an overview of both of these problems and outlines solution schemes to overcome the corresponding bottlenecks.

Thermal and Power Delivery Challenges in 3D ICs

Silicon Interposer provides very high density interconnect combining through Silicon vias and fine wiring. The concept reported in this paper is implementing integrated power supply layers with decoupling metal insulator metal decoupling capacitor to enhance signal integrity. In addition an upscale damascene process was used to fabricate high density and high bandwidth routing interconnect. A detailed characterization of the warpage behavior along the processing steps and electrical characterization of interposer TSV and BEOL are reported.

Interposer technology for high band width interconnect applications

A silicon interposer with an integrated with SrTiO3 (STO) thin film capacitor that decreases switching noise in high-speed digital circuits has been developed, along with a process to fabricate it. The process for fabricating the capacitor was optimized to reduce the defect density. The identified optimal process conditions are sputter-depositing the STO at 400 °C and using Ru as a bottom electrode. An large-scale integration chip is stacked on the Si interposers using chip-to-wafer bonding, and through-silicon vias (TSVs) are then formed in the interposer. This stacking enables a 50 μm-thick Si interposer to be inserted between a chip and a printed wiring board (PWB). A maximum capacitance density of 2.5 F/cm2 was achieved for a 60-nm-thick STO capacitor in a 20 × 20 mm2 area with 9000 TSVs (50- diameter; 50- depth). The capacitance of slightly more than 1 F in interposer-chip stack samples with 1600 TSVs remained constant during a thermal testing on PWBs for up to 1000 cycles.

A Silicon Interposer With an Integrated ${\rm SrTiO}_{3}$ Thin Film Decoupling Capacitor and Through-Silicon Vias

A reliable metal-insulator-metal (MIM) capacitor exceeding 250nF has been integrated into the copper/low-K backend of a high-performance 90nm SOI technology The reduction of supply grid voltage transients has enhanced microprocessor performance by approximately 10% without increasing the chip area or power consumption

Application of on-chip MIM decoupling capacitor for 90nm SOI microprocessor

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Application of on-chip MIM decoupling capacitor for 90nm SOI microprocessor