D. Sing
Freescale Semiconductor
5 Papers
132 Citations
D. Sing is an academic researcher from Freescale Semiconductor. The author has contributed to research in topics: CMOS & Field-effect transistor. The author has an hindex of 3, co-authored 5 publications.
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Papers
CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)
Leo Mathew,Yang Du,Aaron Thean,Michael A. Sadd,A. Vandooren,Colita Parker,Tab A. Stephens,Rode R. Mora,R. Rai,M. Zavala,D. Sing,S. Kalpat,J. Hughes,Rob Shimer,S. Jallepalli,G.O. Workman,W. Zhang,Jerry G. Fossum,Bruce E. White,Bich-Yen Nguyen,J. Mogab +20 more
- 04 Oct 2004
TL;DR: In this article, perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated for mixed-signal applications and used as signal mixer.
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Inverted T channel FET (ITFET) - Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45nm and beyond CMOS.
Leo Mathew,Michael A. Sadd,S. Kalpat,M. Zavala,Tab A. Stephens,R. Mora,S. Bagchi,Colita Parker,J. Vasek,D. Sing,R. Shimer,L. Prabhu,G.O. Workman,G. Ablen,Z. Shi,J. Saenz,Byoung W. Min,David Burnett,Bich-Yen Nguyen,J. Mogab,M.M. Chowdhury,W. Zhang,Jerry G. Fossum +22 more
- 05 Dec 2005
TL;DR: In this article, the authors proposed a novel CMOS IT-FET (inverted T channel FET) architecture that takes advantage of both vertical and horizontal thin-body devices.
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Defect passivation with fluorine in a Ta/sub x/C/ high-K gate stack for enhanced device threshold voltage stability and performance
H.-H. Tseng,Philip J. Tobin,E.A. Hebert,S. Kalpat,M. Ramon,L. R. C. Fonseca,Z.X. Jiang,James K. Schaeffer,Rama I. Hegde,Dina H. Triyoso,David C. Gilmer,W.J. Taylor,C. Capasso,Olubunmi O. Adetutu,D. Sing,J. Conner,E. Luckowski,B.W. Chan,A. Haggag,S. Backer,R. Noble,M. Jahanbani,Y.H. Chili,Bruce E. White +23 more
- 05 Dec 2005
TL;DR: Using a novel fluorinated TaxCy/high-k gate stack, this article showed breakthrough device reliability and performance improvements, which is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern.
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ITFET: Inverted T Channel FET, A Novel Device architecture and circuits based on the ITFET
Leo Mathew,Michael A. Sadd,S. Kalpat,M. Zavala,Tab A. Stephens,Rode R. Mora,Raj Rai,Colita Parker,J. Vasek,D. Sing,R. Shinier,L. Prabhu,G.O. Workman,G. Ablen,Zhonghai Shi,J. Saenz,Byoung W. Min,David Burnett,Bich-Yen Nguyen,J. Mogab,M.M. Chowdhury,W. Zhang,Jerry G. Fossum +22 more
- 14 Aug 2006
TL;DR: Simulated performances of the ITFET devices predict these devices can meet the 45nm and 32nm device performance.
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Performance Enhancement via Laser Anneal-Based RS/D Reduction in PD/SOICMOS
Vishal P. Trivedi,Gregory S. Spencer,Paul A. Grudowski,J. Liu,D. Sing,P. Choi,S. Parsons,Venkat R. Kolagunta,Jon D. Cheek +8 more
- 01 Oct 2006
TL;DR: In this article, the first application of LSA to 35nm gate length, high-performance PD/SOI CMOS with dual etch stop layer (dESL) stressors and NiSi was presented, showing 10% (4%) nFET (pFET) onstate current (Ion) enhancement and non-self-heated Ion=1520/1160muA/mum (880/630muA)/mum.
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