A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.

Three-dimensional memory array and method of fabrication

AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD). In another method the insulating layer is sputtered onto the top surface of the HEMT in a sputtering chamber.

Insulating gate AlGaN/GaN HEMT

A review of recent and current work on microwave FET's and amplifiers is presented, and an extensive bibliography of recent articles is appended (250 references). First, the various FET structures (MRSFET's, JFET's, and IGFET's) and their performances are reviewed. Second, the principle of operation is outlined for Si- and GaAs-MESFET's; the basic device physics, equivalent circuit, high-frequency limitations, and noise behavior are treated. Third, the design principles and performance of microwave MESFET amplifiers are summarized.

Microwave Field-Effect Transistors--1976

The electrical characteristics of ion implanted compound semiconductors

An electrical capacitor having a stack of at least two metal layers separated by a dielectric layer disposed between a pair of cover foils with the metal layers being offset in a staggered relationship characterized by a pair of connecting wires embedded in one of the cover foils with at least one portion of each wire projecting through the cover foil and in electrical contact with the metal layer disposed therebeneath. In embodiments, the wires may have a serpentine shape which may be formed during the method of fusing the wires into the cover layer or foil which shape provides portions projecting through the metal layer to be fused to the opposite cover foil while adjacent portions of the wires form the electrical connection.

Electrical capacitors and method of making same

A method for manufacturing a field effect transistor which includes one more spacer provided in the gate recess adjacent the drain sidewall than adjacent the source sidewall in the contact such that a gate metallization is displaced asymmetrically toward a source side sidewall of the recess; and method for manufacturing same wherein oblique vapor deposition of an auxiliary layer into a recess for the gate region makes it possible for a spacer therein at the source side to be removed whereas a spacer of the drain side remains in place, such that the subsequent gate metallization is positioned closer to the source than to the drain.

Method for manufacturing a field effect transistor

Electrical components, particularly RC networks, are produced by a method in which a thermoplastic carrier foil supports one or more electrically conductive layers with insulating and/or dielectric layers between the conductive layers. In the method an electrically conductive layer or layers is or are applied to a carrier foil and the electrically conductive layers are provided with at least one contacting area for receiving a contacting wire. The contacting areas include a metal having a surface conductivity of at least 3 mho. The carrier foil is covered at least in the region of the contacting areas with a thermoplastic covering foil and an appropriate number of contacting wires, which may also serve as electrical leads, are fed above the covering layer at the location of the contacting areas, heated and impressed into the stack arrangement at at least points along its length through the covering foil and into one or more of the contacting areas to form therewith a mechanically stable and electrically conductive connection.

Production of electrical components, particularly RC networks

A co-sputtering process is characterized which allows the deposition of WSi0.4 layers for Schottky gates of GaAs self-aligned MESFETs. The process parameters were optimized to yield films with low stress, good adhesion and a high interface stability during 800°C n+ implant activation anneal. The good diffusion barrier properties of the Schottky metal can be attributed to the amorphous nature of the film. This implies a natural explanation of the optimum film composition. Employing various analytical methods the gate metal/GaAs interface was characterized after 800°C anneal. I−V diode measurements were performed to obtain contact electrical properties such as barrier height and ideality factor. MESFETs with different channel implants down to 10 keV were fabricated to confirm the good stability of the Schottky contact.

WSix refractory gate metal process for GaAs MESFETs

A MESFET is disclosed wherein a gallium arsenide semiconductor material is doped. The doping magnitude differs in the source area, drain area, and in the gate area. An increase of the dielectric strength without an increase of parasitic resistances is provided. In the manufacture of the MESFET, shadowing techniques are employed to vary the doping magnitudes.

Method of making a MESFET having same type conductivity for source, drain, and gate regions

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