We address degradation aspects of lattice-matched unpassivated InAlN/GaN high-electron-mobility transistors (HEMTs). Stress conditions include an off-state stress, a semi-on stress (with a partially opened channel), and a negative gate bias stress (with source and drain contacts grounded). Degradation is analyzed by measuring the drain current, a threshold voltage, a Schottky contact barrier height, a gate leakage and an ideality factor, an access, and an intrinsic channel resistance, respectively. For the drain-gate bias < 38 V parameters are only reversibly degraded due to charging of the pre-existing surface states. This is in a clear contrast to reported AlGaN/GaN HEMTs where an irreversible damage and a lattice relaxation have been found for similar conditions. For drain-gate biases over 38 V InAlN/GaN HEMTs show again only temporal changes for the negative gate bias stresses; however, irreversible damage was found for the off-state and for the semi-on stresses. Most severe changes, an increase in the intrinsic channel resistance by one order of magnitude and a decrease in the drain current by similar to 70%, are found after the off-state similar to 50 V drain-gate bias stresses. We conclude that in the off-state condition hot electrons may create defects or ionize deep states in the GaN buffer or at the InAlN/GaN interface. If an InAlN/GaN HEMT channel is opened during the stress, lack of the strain in the barrier layer is beneficial for enhancing the device stability.

Analysis of degradation mechanisms in lattice-matched InAlN/GaN high-electron-mobility transistors

We present the technology and performance of InAlN/AlN/GaN MOS HEMTs with gate insulation and surface passivation using Zr or Hf . About 10-nm-thick high- dielectrics were deposited by MOCVD before the ohmic contact processing. Plasma pretreatment allowed the reduction of the temperature of the ohmic contact annealing at 600degC. The insulation and passivation of 2-m gate-length MOS HEMTs lead to a gate leakage current reduction by four orders of magnitude and a 2.5 increase of the pulsed drain-current if compared with a Schottky barrier (SB) HEMT. A dc characterization shows 110 mS mm transconductance and 0.9 A mm drain--currents that represent improvements in comparison to the similar SB HEMT and that is explained by a mobility-dependent carrier depletion effect.

Technology and Performance of InAlN/AlN/GaN HEMTs With Gate Insulation and Current Collapse Suppression Using Zr $\hbox{O}_{\bm 2}$ or Hf $\hbox{O}_{\bm 2}$

InAlN/GaN two-dimensional electron gas (2DEG) heterostructures were successfully grown by metalorganic chemical vapor deposition. X-ray photoelectron spectroscopy and X-ray diffraction measurements revealed that the barrier layer consists of a ternary In0.18Al0.82N alloy, a composition nearly lattice-matched to GaN. The bandgap energy of the In0.18Al0.82N barrier layer was estimated to be approximately 4.3 eV by spectroscopic ellipsometry analysis. Electrical characterization results showed that 2DEG mobility can be improved with the insertion of a thin AlN layer at the InAlN/GaN heterointerface. Very high 2DEG densities of more than 2.6×1013 cm-2 and high 2DEG mobilities of 1170 cm2/(V s) were achieved for InAlN/AlN/GaN structures with the barrier thickness of more than 15 nm. These 2DEG properties are almost equal to the best ones ever reported for InAlN/GaN 2DEG structures.

https://iopscience.iop.org/article/10.1143/APEX.1.081102/pdf

Metalorganic Chemical Vapor Deposition and Material Characterization of Lattice-Matched InAlN/GaN Two-Dimensional Electron Gas Heterostructures

Hot-electron temperature (T-e) in InAlN/GaN high-electron-mobility transistors (HEMTs) was determined using electroluminescence spectroscopy as a function of gate voltage and correlated with the Te distribution determined by hydrodynamic simulations. Good agreement between measurement and simulations suggests that hot electrons can locally reach temperatures of up to 30 000 K at V-ds = 30 V, i.e., two to three times higher than that typically obtained for similar AlGaN/GaN HEMTs. The consequence of such high Te in InAlN/GaN HEMTs is illustrated by electrical stressing in OFF and semi-ON state at V-gd = 100 V. Prominent channel degradation was observed for devices stressed in semi-ON state, suggesting hot-electron driven degradation. Threshold voltage and drain current transient analyses indicate that hot electrons increase the density of traps in the GaN channel underneath the gate as well as surface/interface traps located in the gate-to-drain access region.

https://www.iue.tuwien.ac.at/pdf/ib_2014/hashed_links/ep4PCgrdGnGazWmXzOrCY_us.pdf

Hot-Electron-Related Degradation in InAlN/GaN High-Electron-Mobility Transistors

Design considerations and performance of n++ GaN/InAlN/AlN/GaN normally off high-electron mobility transistors (HEMTs) are analyzed. Selective and damage-free dry etching of the gate recess through the GaN cap down to a 1-nm-thick InAlN barrier secures positive threshold voltage, while the thickness and the doping of the GaN cap influence the HEMT direct current and microwave performance. The cap doping density was suggested to be 2 × 1020 cm-3. To screen the channel from the surface traps, the needed cap thickness was estimated to be only 6 nm. Design is proved by an experiment showing a constant value of the HEMT dynamical access resistance, while a single-pulse experiment indicated almost collapse-free performance. On the other hand, it is found that the n++ GaN cap does not contribute to the HEMT drain current conduction, nor does it provide a path for the off-state breakdown. HEMTs with a gate length of 0.25 μm and a 4-μm source-to-drain distance show a drain-to-source current of 0.8 A/mm, a transconductance of 440 mS/mm, a threshold voltage of ~0.4 V, and a cutoff frequency of 50 GHz. A thin and highly doped GaN cap is also found to be suitable for the processing of normally on HEMTs by adopting the nonrecessed gate separated from the cap by insulation.

Proposal and Performance Analysis of Normally Off $ \hbox{n}^{++}$ GaN/InAlN/AlN/GaN HEMTs With 1-nm-Thick InAlN Barrier

Gate and drain-lag effects are studied in (GaN)/InAlN/GaN and InAlN/AlN/GaN HEMTs grown on sapphire. Electron trapping on the surface states between the gate and the drain forming the net negative charge up-to similar to 2 x 10(13) cm(-2) is found to be responsible for the gate-lag effect in the (GaN)/InAlN/GaN HEMTs. If the polarization charge at the device surface is decreased by GaN capping, then density of the trapped charge is not changed, however the electron de-trapping process becomes faster. The drain-lag effect is caused by electron injection and trapping in the source-gate area reaching similar to 1 x 10(13) cm(-2) of the trapped charge in the steady state. In the studied voltage range the InAlN/AlN/GaN HEMT is shown to be gate-lag-free suggesting that this parasitic transient can be avoided if thin AlN is used in the epi-layer growth sequence. It is assumed that this breakthrough quality relates to the decreased or even reverted electric field in the MAIN layer if AlN is inserted. Surface states need not to be generated in this case. (c) 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Gate-lag and drain-lag effects in (GaN)/InAlN/GaN and InAlN/AlN/GaN HEMTs

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Gate-lag and drain-lag effects in (GaN)/InAlN/GaN and InAlN/AlN/GaN HEMTs