A fully-integrated, silicon photonic transceiver is demonstrated in a silicon-on-insulator process using photonic microring resonator modulators for low power consumption. The trade-offs between bandwidth and extinction ratio are discussed and motivate the use of transmit pre-emphasis for ring modulators to increase the interconnect data rate. The transmitter and receiver is demonstrated to data rates of 25 Gb/s with a BER of 10 ^-12. The total power consumption of the transceiver is 256 mW and demonstrates a link efficiency of 10.2 pJ/bit excluding laser power. At 25 Gb/s, the driver operates at 7.2 pJ/bit.

A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process

A chip-to-chip optical interconnect includes a substrate, an optoelectronic die, and a waveguide structure The substrate includes an optical via passing through the substrate The optoelectronic die is disposed on the substrate and aligned to optically communicate through the optical via A waveguide structure is positioned proximate to the substrate and aligned with the optical via to communicate optical signals with the optoelectronic die through the optical via

Chip-to-chip optical interconnect

Terabus is based on a silicon-carrier interposer on an organic card containing 48 polymer waveguides. We have demonstrated 4/spl times/12 arrays of low power optical transmitters and receivers, operating up to 20 Gb/s and 14 Gb/s per channel respectively.

Chip-to-chip optical interconnects

Local interconnect architectures are at a cusp in which advances in throughput have come at the expense of power and latency. Moreover, physical limits imposed on dissipation and packaging mean that further advances will require a new approach to interconnect design. Although latency in networks has been the focus of the High-Performance Computing architect and of concern across the computer community, we illustrate how an evolution in the common PCI interconnect architecture has worsened latency by a factor of between 3 and 25 over earlier incarnations.

/pdf/motivating-future-interconnects-a-differential-measurement-408qlk0ngz.pdf

Motivating future interconnects: a differential measurement analysis of PCI latency

A polymer waveguide with 4-channel graded-index circular cores is fabricated by the preform method. Very low loss (0.028 dB/cm at a wavelength of 850 nm) and high bandwidth (83 Gbps for 1 m, estimated) properties are experimentally demonstrated by the new waveguide for the first time. By densely aligning the cores during the preform fabrication, a waveguide with a pitch size of 56 μm and a core diameter of 50 μm is obtained, which is expected to be utilized in high-speed and high-density parallel optical interconnections.

/pdf/polymer-waveguide-with-4-channel-graded-index-circular-cores-f8kff65onr.pdf

Polymer waveguide with 4-channel graded-index circular cores for parallel optical interconnects

Terabus is based on a chip-like optoelectronic packaging structure (Optochip) assembled directly onto an organic card with integrated waveguides (Optocard). To-date, Terabus has demonstrated 4times12-array optical transmitters and receivers operating up to 20 Gb/s and 14 Gb/s per channel

Terabus: a chip-to-chip parallel optical interconnect

Terabus is an optical link for parallel chip-to-chip interconnects operating in the 0.5-1 Tb/s range. It is based on a chip-like optoelectronic packaging structure (optochip) assembled directly onto an organic card with integrated waveguides (optocard).

Terabus: A Waveguide-Based Parallel Optical Interconnect

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Terabus: a chip-to-chip parallel optical interconnect

Terabus: A Waveguide-Based Parallel Optical Interconnect