A digital channelized receiver is presented for the interception of a wide variety of signals of complex structure, including those with low probability of interception. The receiver is designed from the perspective of the time-frequency analysis. It uses an extended time-frequency representation based on the noncoherent integration of the short-time Fourier transform (STFT) on which the detection system and the encoder work. The encoder includes robust frequency estimation, automatic modulation recognition, and clustering, to handle broadband and simultaneous signals and to prevent out-of-channel detections (a typical phenomenon in channelized receivers). The receiver has been evaluated for a wide range of signals and shows a good performance in terms of detection, estimation, and processing of simultaneous signals. Signals collected from real-life systems and synthetic signals have been utilized.

Digital channelized receiver based on time-frequency analysis for signal interception

A direct digitization approach greatly reduces the hardware requirements in traditional front end design. Further, the hardware that has been eliminated is typically the source of a number of potential difficulties including age-based, temperature-based, and/or nonlinear performance. This paper presents a case study on the design and implementation of direct digitization Global Positioning System (GPS) receiver front end. First, sensitivity and dynamic range issues for a generic front end are discussed with particular attention given to the unique requirements in the direct digitization approach. Second, two GPS front end implementations are compared. The first is the direct digitization of the input signal at radio frequency (RF) as is the case in the true digital receiver or software radio. The second uses a more standard approach of downconverting the input signal to an intermediate frequency (IF) for further processing of digitization. Experimental data is presented which characterizes the relative signal-to-noise ratio for both implementations as well as the results of initial acquisition processing of true GPS data.

Design and implementation of a direct digitization GPS receiver front end

This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed in depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms.

/pdf/implementing-fft-based-digital-channelized-receivers-on-fpga-34h2guzryn.pdf

Implementing FFT-based digital channelized receivers on FPGA platforms

This paper discusses the advantages of digital beamforming (DBF), both generally and specific to satellite communications antennas, and briefly describes some of its early implementations. A discussion of recent advances in analog-to-digital converter (ADC) technology is followed by a description of the basic DBF functionality and tradeoffs in functional partitioning in a DBF array. The application of DBF to a heritage phased array is described to illustrate the benefits of DBF for spaceborne phased arrays. Finally, technology options for DBF implementation in a spaceborne phased array are considered.

A New Era in Elemental Digital Beamforming for Spaceborne Communications Phased Arrays

This paper reports the impact of digital signal processing on microwave receiver technology. The majority of modern receiver designs are based on digital technology. Wide-and narrow-band receivers are presented. The wide-band receivers cover approximately 1-GHz instantaneous bandwidth and are used to intercept radar pulses. Current narrow-band receivers cover up to 50-MHz instantaneous bandwidth and are primarily used for receiving communication signals. Two approaches for wide-band receiver design are discussed. One is the conventional digital receiver. The other one is called the monobit receiver, which has slightly inferior performance in some respects, but can be built on a single chip. Narrow-band receivers are best implemented in software because they can more adapt to changes. Two types of receivers are discussed. One is the software Global Positioning System receiver. The other one is called a transform-domain communication system. The object of this system is to avoid interference in a hostile communication environment.

Digital microwave receiver technology

An approach is presented to realizing a digital channelized receiver for signal intercept applications that provides a hardware efficient implementation of a uniform filter bank in which the number of filters K is greater than the decimation factor M. The proposed architecture allows simple channel arbitration logic to be used and provides reliable instantaneous frequency measurements, even in adjacent channel crossover regions. In the proposed implementation of the filter bank, K is related to M by K=FM where F is an integer. It is shown that the optimum selection of F allows the instantaneous frequency measurement to be made in the channel crossover region and the arbitration function to be based solely on the instantaneous frequency measurement. The development of a filter bank structure which combines the flexibility of the short-time Fourier transform (STFT) with the implementation efficiency of the polyphase filter bank decomposition, meeting these requirements and leading to a hardware-efficient implementation, is presented.

A hardware-efficient, multirate, digital channelized receiver architecture

An analysis of the relationship between a linear amplifier chain and an analog-to-digital converter (ADC) in a digital microwave receiver, with respect to sensitivity and dynamic range issues, is presented. The effects of gain, third-order intermodulation products and ADC characteristics on the performance of the receiver are illustrated and design criteria for the linear amplifier chain (given a specified ADC) are developed. A computer program is included which calculates theoretical receiver performance based on gain and third-order intermodulation product selections. Experimental results are also presented and compared with theoretical values. >

/pdf/analysis-of-the-linear-amplifier-analog-digital-converter-3e20felit9.pdf

Analysis of the linear amplifier/analog-digital converter interface in a digital microwave receiver

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A hardware-efficient, multirate, digital channelized receiver architecture

Analysis of the linear amplifier/analog-digital converter interface in a digital microwave receiver