Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

This paper examines a number of stochastic computational elements employed in artificial neural networks, several of which are introduced for the first time, together with an analysis of their operation. We briefly include multiplication, squaring, addition, subtraction, and division circuits in both unipolar and bipolar formats, the principles of which are well-known, at least for unipolar signals. We have introduced several modifications to improve the speed of the division operation. The primary contribution of this paper, however, is in introducing several state machine-based computational elements for performing sigmoid nonlinearity mappings, linear gain, and exponentiation functions. We also describe an efficient method for the generation of, and conversion between, stochastic and deterministic binary signals. The validity of the present approach is demonstrated in a companion paper through a sample application, the recognition of noisy optical characters using soft competitive learning. Network generalization capabilities of the stochastic network maintain a squared error within 10 percent of that of a floating-point implementation for a wide range of noise levels. While the accuracy of stochastic computation may not compare favorably with more conventional binary radix-based computation, the low circuit area, power, and speed characteristics may, in certain situations, make them attractive for VLSI implementation of artificial neural networks.

Stochastic neural computation. I. Computational elements

This thesis develops a theoretical model for the wiring complexity of wide classes of systems, relating the degree of connectivity of a circuit to the dimensionality of its interconnect technology. This model is used to design an efficient, hierarchical interconnection network capable of accommodating large classes of circuits. Predesigned circuit elements can be incorporated into this hierarchy, permitting semi-customization for particular classes of systems (e.g., photoreceptors included on vision chips). A polynomial-time programming algorithm for embedding the desired circuit graph onto the prefabricated routing resources is presented, and is implemented as part of a general design tool for specifying, manipulating and comparing circuit netlists.
This thesis presents a system intended to facilitate analog circuit design. At its core is a VLSI chip that is electrically configured in the field by selectively connecting predesigned elements to form a desired circuit, which is then tested electrically. The system may be considered a hardware accelerator for simulation, and its large capacity permits testing system ideas, which is impractical using current means. A fast-turnaround simulator permitting rapid conception and evaluation of circuit ideas is an invaluable aid to developing an understanding of system design in a VLSI context.
We have constructed systems using both reconfigurable interconnection switches and laser-programmed interconnect. Prototypes capable of synthesizing circuits consisting of over 1000 transistors have been constructed. The flexibility of the system has been demonstrated, and data from parametric tests have proven the validity of the approach.
Finally, this thesis presents several new circuits that have become key components in many analog VLSI systems. Fast, dense and provably safe one-phase latches and hierarchical arbiters are presented, as are a low-noise analog switch, an isotropic novelty filter, a dense, active high-resistance element, and a subthreshold differential amplifier with a large linear input range.

http://www.ini.uzh.ch/~tobi/wiki/lib/exe/fetch.php?media=masssivilottithesiscaltech1991.pdf

Wiring considerations in analog VLSI systems, with application to field-programmable networks

This paper presents a new methodology for the hardware implementation of neural networks (NNs) based on probabilistic laws. The proposed encoding scheme circumvents the limitations of classical stochastic computing (based on unipolar or bipolar encoding) extending the representation range to any real number using the ratio of two bipolar-encoded pulsed signals. Furthermore, the novel approach presents practically a total noise-immunity capability due to its specific codification. We introduce different designs for building the fundamental blocks needed to implement NNs. The validity of the present approach is demonstrated through a regression and a pattern recognition task. The low cost of the methodology in terms of hardware, along with its capacity to implement complex mathematical functions (such as the hyperbolic tangent), allows its use for building highly reliable systems and parallel computing.

A New Stochastic Computing Methodology for Efficient Neural Network Implementation

In massively parallel computational tasks, such as pattern recognition, conventional computing architectures have insufficient power efficiency for energy constrained environments This has made alternative architectures, such as neuromorphic computing, increasingly attractive Oscillatory neural networks (ONNs) are one promising architecture, but efficient hardware implementations have been limited by shortcomings in CMOS technology, specifically in the efficient implementation of oscillators and synaptic weights The authors have recently demonstrated that metal-oxide based resistive switching (RRAM) structures can be engineered to create low-power, scalable, voltage-controlled oscillators that utilize inherent meta-stability in the device This work proposes an RRAM-based ONN that couples oscillatory “neurons” through weighted “synapses” using oscillator phase as the state-variable This paper demonstrates a robust architecture using only a few logic gates per neuron to implement phase initialization and locking of these oscillators, and demonstrate their capability to identify stored patterns from noisy inputs Using measured characteristics of RRAMs as oscillators and programmable resistors, compact models are derived and used to simulate both an 8-neuron and 20-neuron network

Oscillatory Neural Networks Based on TMO Nano-Oscillators and Multi-Level RRAM Cells

An approach to solving the two most serious shortcomings of previous artificial neural network implementations is discussed. A flexible architecture that permits the realization of arbitrary network topologies and dimensions is presented. Furthermore, the performance of this architecture is independent of the size of the network and permits the processing of typically 100000 patterns per second. The key innovation is the representation of neuron activations and synaptic weights as stochastic functions of time, leading to efficient implementations of the synapses. High densities of synapses per silicon area, exceeding even analog implementations, have been achieved. Finally, the neuron activations are represented digitally, as are the synaptic computations, thereby permitting fabrication of digital neural network architectures using a variety of standard, low-cost semiconductor processes. A pair of general-purpose chips (SU3232 and NU32) that permit post facto construction of neural networks of arbitrary topology and virtually unlimited dimensions is presented

A digital neural network architecture for VLSI

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A digital neural network architecture for VLSI