The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects.

/pdf/rationale-and-challenges-for-optical-interconnects-to-5clh2238g9.pdf

Rationale and challenges for optical interconnects to electronic chips

A combined optoelectronic and optomechanical packaging technique for the construction of snap-together free-space optical interconnect systems is described. The modules integrate relaying and routing functions by use of transparent optical molded plastic, which can achieve sufficient alignment precision that further adjustment is not required during system assembly. Methods to integrate the optoelectronic chips, such as vertical-cavity surface-emitting laser and receiver arrays with these plastic optical modules are described. Other chips can also be integrated to form optoelectronic multichip modules. These modules can also be designed to accommodate coupling to or from optical fiber arrays. A test-bed system to demonstrate the concept was assembled to a lower precision by use of conventional machining techniques.

Plastic modules for free-space optical interconnects

The vertical-cavity surface-emitting laser (VCSEL) is emerging as a key element for next-generation information processing systems and technologies. This laser has the ease of manufacture of the light-emitting diode and the versatility of the conventional edge-emitting laser for high-speed interconnect applications in communication networks. Its size, manufacturability, and potential ease of heterogeneous integration with electronics promise a range of applications that have yet to be explored. The paper outlines the history of the development of the surface-emitting laser and the role that fortuitous timing and the creation of an infrastructure have played in its successful development.

A historical perspective of the development of the vertical-cavity surface-emitting laser

The fundamental reasons that determine the tolerance of free-space optical interconnect systems to misalignment are considered. By evaluation of the overlap of single-mode optical beams in the presence of misalignment it possible to determine an optimum beam configuration. It is shown that for any level of misalignment there is an optimum beam diameter that maximizes the coupling of light through the system. Many interconnect systems are not single mode throughout, so the analysis is extended to cover multimode systems. It is shown that, in principle, any level of misalignment can be accommodated by use of multimode beams, although at the cost of reduced channel density. It is shown that the presence of misalignment will mean that the number of channels that can be supported by an interconnect reduces with the length of the interconnect. As possible candidates for passively aligned systems, three example optical systems are analyzed by use of the methods developed.

Tolerance of optical interconnections to misalignment.

A theoretical model for an optoelectronic modulation doped thyristor is developed. The thyristor incorporates two modulation doped interfaces and as such it forms a technology base for both p- and n-type modulation doped transistors. The thyristor current–voltage (I–V) relations are developed based upon the thermionic current flow over the modulation doped junctions providing the feedback to initiate switching and upon the feedback current between quantum wells which stabilizes the device in the on state. The dependence of the carrier densities in the quantum wells upon bias are shown to be a unique property of the device. The I–V dependence is shown as a function of the critical device dimensions which are key design parameters for optoelectronic integrated circuits. The validity of the model and the structure is confirmed by comparison to the measured I–V characteristic.

Current–voltage relations for the dual channel double heterostructure optoelectronic switch

The architecture, smart pixel array chip design, and optical design of an intelligent free-space digital optical backplane for ATM switching are presented. The smart pixel chip uses reflective SEED (self-electrooptic effect device) optical modulators and detectors flip-chip bonded to CMOS circuitry. This chip is one of the most complex designs ever reported in this technology, and it operates at a simulated backplane clock rate of 125 MHz. The low-loss optical system employs f/4 diffractive minilenses and microlenses to interconnect clusters of smart pixels, and it is shown to allow 2060 connections per chip if 1-cm2-sized smart pixel chips are used. This gives a predicted bisection bandwidth of around 1 Tb/s across a 10-in circuit board edge for a full-sized system.

/pdf/an-atm-based-intelligent-optical-backplane-using-cmos-seed-49wvxmd2ru.pdf

An ATM-based intelligent optical backplane using CMOS-SEED smart pixel arrays and free-space optical interconnect modules

A set of optics suitable for interconnecting and powering reflective hybrid-SEEDs in a free-space optical backplane has been presented. Detailed design has been conducted to demonstrate that the optics meet the constraints both of required performance, and of available fabrication. The design process has shown that with given hybrid-SEED design rules a smart pixel density of 515/cm/sup 2/ can be supported on a 1 cm/sup 2/ chip.

http://ieeexplore.ieee.org/iel3/3845/11213/00540745.pdf

Optical interconnect module extensible to 10,000 parallel channels for a smart-pixel optical backplane

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An ATM-based intelligent optical backplane using CMOS-SEED smart pixel arrays and free-space optical interconnect modules

Optical interconnect module extensible to 10,000 parallel channels for a smart-pixel optical backplane