In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

/pdf/finfets-and-other-multi-gate-transistors-541arp307w.pdf

FinFETs and Other Multi-Gate Transistors

This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context

PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation

: This report is addressed to all SPICE2 users involved in the design of MOS (Metal Oxide Semiconductor) IC's (Integrated circuits). The material contained herein serves as an addition to the SPICE2.G User's Guide. The device and model parameters documented refer to the SPICE2.G release versions from the University of California, Berkeley and obsolete the information contained in the SPICE2 MOS Modeling Handbook which is valid for the SPICE2.D release versions. The impact of MOS IC s in both analog and digital applications as well as the decreasing dimensions of the single transistors enabled by advances in processing have made it necessary to refine the models and to provide more information about each device as it appears on the circuit layout. Associated with each MOSFET is a drain and source-junction sidewall capacitance (which has a different voltage dependence than the bottom of the diffusion) and a parasitic series resistance. These are unique to a certain geometry. At the model level there are effects which become important as the channel length and width go below 10um. A thorough description of all parameters appearing on the element (device) card and model card is contained in Sec. 2. In SPICE2.G there are three different MOS models available to the user. The Level 1 model is the simple Shichman-Hodges model implemented according to Nagel s SPICE2: A Computer Program to Simulate Semiconductor Circuits. This first order model has been found necessary for checking out the correctness of hand calculations when understanding or developing new circuits. The Level 2 model is an analytical one-dimensional model which incorporates most of the second-order effects of small-size devices. The Level 3 model is a semi-empirical model described by a set of parameters which are defined by curve-fitting rather than physical background.

/pdf/the-simulation-of-mos-integrated-circuits-using-spice2-23aput6sm0.pdf

The Simulation of MOS Integrated Circuits Using SPICE2

Device physics of organic electrochemical transistors

Two methods have been developed for analyzing MOS transients. One method is analytical and uses the quasi-static approximation. It is useful when the stray capacitance dominates MOS transient performance. The second method is numericaf and uses a new boundary value method which can be applied over a wide range of operating speeds. This method includes secondary effects and nonuniform doping. The validity and Iimits for both methods are verified by comparison with measurements. Transit-time delay and charge-pumping effects are also analyzed using the numerical method. Examples of short-channel behavior of MOS devices are included.

Transient Analysis of MOS Transistors

Two methods have been developed for analyzing MOS transients. One method is analytical and uses the quasi-static approximation. It is useful when the stray capacitance dominates MOS transient performance. The second method is numerical and uses a new boundary value method which can be applied over a wide range of operating speeds. This method includes secondary effects and nonuniform doping, The validity and limits for both methods are verified by comparison with measurements. Transit-time delay and charge-pumping effects are also analyzed using the numerical method. Examples of short-channel behavior of MOS devices are included.

Transient analysis of MOS transistors

A new model for computer simulation of capacitance effects in MOS transistors is presented. Transient currents are found directly from the charge distribu- tion in the device rather than from capacitances. The effective capacitances which result are non-reciprocal. The model guarantees conservation of charge and includes bulk capacitances. Several circuit examples are considered.

A Charge-oriented Model For MOS Transistor Capacitances

TA-A7 A charge-oriented model for MOS transistor capacitances

A new model for computer simulation of capacitance effects in MOS transistors is presented. Transient currents are found directly from the charge distribution in the device rather than from capacitances. The effective capacitances which result are nonreciprocal. The model guarantees conservation of charge and includes bulk capacitances. Several circuit examples are considered.

A charge-oriented model for MOS transistor capacitances

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