Multiprocessor arrays have the property of regularity, enabling a low-cost VLSI implementation. However, multiprocessor systems with a fixed structure tend to be error prone and restricted to specialized applications, which makes them less attractive to the semiconductor industry. Consequently, reconfigurability and fault-tolerance are desirable features of a multiprocessor array. A multiprocessor array with a flexible structure can be adapted to many applications and may restructure itself upon failure of a processor, to avoid using faulty processors.The objective of this work is to demonstrate the feasibility of a multiprocessor array having these properties. An example of such an array is introduced, and distributed structuring algorithms for it are presented. A novel strategy for internal testing and for identification of faulty processors is developed, and the structuring algorithms are modified to accommodate faulty processors.

A reconfigurable and fault-tolerant VLSI multiprocessor array

An overview is presented of low-pressure chemical vapor deposition and its applicability to VLSI processing for depositing thin films of insulators, semiconductors, and metals. The major contributions of low-pressure chemical vapor deposition to VLSI technology are its capability for economically producing films with superior uniformity, high purity, and excellent step coverage-factors essential for achieving the very high device reliability and high product yield required in the manufacturing of VLSI devices. Specific examples from the recent literature are reviewed to exemplify how the technique has been utilized to date in solid-state device technology. Applications of films produced by low-pressure reactive plasma chemical vapor deposition are also included.

Low-pressure chemical vapor deposition for very large-scale integration processing&#8212;A review

This paper considers the organization of certain multicomputer systems with a particular type of dynamic architecture. The system allows one to reconfigure via software available hardware resources (widths of processors, memories, and I/O units), forming computers with different word sizes. A multicomputer system is formed from identical dynamic computer groups. Each group may assume a variety of architectural states which are distinct from each other by the number and sizes of concurrent computers. To construct one dynamic computer group, one uses a universal building module, an 8-bit microprocessor on an LSI chip, and standard memory units. This paper considers basic principles of dynamic computer group implementation: organization of parallel (for words) and serial (for instructions) exchange between primary memory and processor, automatic variation of the time intervals assigned for operations which are executed in differently sized computers, formation of the processor with variable word size, switching from one architectural state to another, scheduling of the memory, and task synchronization.

A Multicomputer System with Dynamic Architecture

Hierarchical design methods are considered to be a means of managing the VLSI design problem. This paper will consider why this problem exists and discuss alternative means that can be used to arrive at a solution. The merits of design methodologies, with emphasis on hierarchical techniques, will be compared with those of automated design approaches. The discussion of hierarchy will lead to the conclusion that the method requires formal abstraction facilities in order to be effective. Hierarchical design methods permit the creation of a new generation of CAD programs that can both give a designer better support and can be much more efficient than the present generation of tools. An example of such a tool, VOILA, will be given.

Hierarchical design methodologies and tools for VLSI chips

Fault tolerance is expected to become the major concern for complex systems consisting of many computing or processing units. Given a basic nonredundant system of computing units, the problems are to determine the minimum extra units and connections required and their structures so that the resulting system would tolerate k faulty units. These problems have been formulated and solved for some special types of systems by Hayes using a graph model. In this paper, we present a procedure for designing an optimal 2-FT (two-fault-tolerant) structure for binary symmetric hierarchical tree systems.

An optimal 2-FT realization of binary symmetric hierarchical tree systems

Advances in LSI technology are beginning to outstrip architectural innovations and their implementation, calling for greater software productivity and development of better design aids.

The Use of LSI Modules in Computer Structures: Trends and Limitations

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The Use of LSI Modules in Computer Structures: Trends and Limitations