A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digit redundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2 n. The computation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2. It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2 log2 n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

An algorithm for performing radix-8 division and square root in a shared hardware is described. To achieve short iteration cycle time, it utilizes an optimized 'next quotient/root prediction PLA' generally used in a radix-4 SRT division with minimal redundancy. In addition, the partial remainder, partial radicand, quotient, and root are generated and saved in redundant forms, thereby eliminating the slow-carry look-ahead adder from the critical path timing of the iteration cycle. This method successfully avoids the need to generate nontrivial divisor/root multiples (3x, 5x, etc.) and also avoids the complex radix-8 next quotient prediction PLA typically used in a conventional radix-8 SRT division. It also shows that a significant amount of hardware sharing can be achieved when square root and division are performed at the same radix. >

Algorithm for high speed shared radix 8 division and radix 8 square root

A novel direct digital frequency synthesis (DDFS) architecture based on the differential CORDIC (DCORDIC) algorithm is presented. The architecture allows digit-level pipelining in the CORDIC angle path by implementing a two-dimensional systolic array. Unlike other DDFS architectures, it incorporates the phase accumulator in the digit-level pipelining framework so that a bottleneck-free datapath throughout the whole system is achieved in a scalable manner. A generic environment that generates fully synthesizable Verilog codes that implement the proposed architecture is created and the physical attributes of the resulting system are discussed.

Digit-pipelined direct digital frequency synthesis based on differential CORDIC

In this work, we present a radix-10 division unit that is based on the digit-recurrence algorithm. The previous decimal division designs do not include recent developments in the theory and practice of this type of algorithm, which were developed for radix-2k dividers. In addition to the adaptation of these features, the radix-10 quotient digit is decomposed into a radix-2 digit and a radix-5 digit in such a way that only five and two times the divisor are required in the recurrence. Moreover, the most significant slice of the recurrence, which includes the selection function, is implemented in radix-2, avoiding the additional delay introduced by the radix-10 carry-save additions and allowing the balancing of the paths to reduce the cycle delay. The results of the implementation of the proposed radix-10 division unit show that its latency is close to that of radix-16 division units (comparable dynamic range of significant) and it has a shorter latency than a radix-10 unit based on the Newton-Raphson approximation

/pdf/a-radix-10-digit-recurrence-division-unit-algorithm-and-4ji9s1p0vx.pdf

A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture

Redundancy, the state of being in excess of what is necessary, as applied in the implementation of computer arithmetic is motivated by three design goals: to improve reliability, to increase speed of operation, and/or to provide structural flexibility. In achieving the first goal, improvement of reliability, hardware redundancy and/or redundant arithmetic codes are applied to the detection and correction of faults. Although this is an increasingly vital area it will not be discussed in this paper. Rather, the focus will be on the other two potential benefits: more specifically, on the judicious use of number systems employing redundancy in representation. A positional number system with fixed radix, r, is redundant if the allowable digit set includes more than r distinct elements, thereby affording alternate representations of a given numeric value. Uniqueness. of representation is sacrificed with hope of greater gains. A novel, rigorous treatment of redundant, radix polynomial representation is included in Reference 1.

Introduction to the Role of Redundancy in Computer Arithmetic

In keeping with the experimental nature of the Illinois Pattern Recognition Computer (ILLIAC III), the arithmetic units are intended to be a practical testing ground for recent theoretical work in computer arithmetic. This paper describes the use of redundant number systems and the design of a structure with which multiplication and division are executed radix 256. The heart of the unit is the stored-sign subtracter, a recently discovered member of the family of borrow-save subtracters and carry-save adders. A cascade of these subtracters, controlled by a multiplier recoder, provides multiplication. The same structure, controlled by a "model division" (a quotient recoder), performs division.

Design of the Arithmetic Units of ILLIAC III: Use of Redundancy and Higher Radix Methods

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Design of the Arithmetic Units of ILLIAC III: Use of Redundancy and Higher Radix Methods