It has been demonstrated that the introduction of HfO2/ TiN gate stacks into CMOS technologies provides the means to continue with traditional device gate length scaling. However, the introduction of HfO2 as a new gate dielectric and TiN as a metallic gate electrode into the gate stack of FETs brings about new challenges for understanding reliability physics and qualification. This contribution summarizes recent advances in the understanding of charge trapping and defect generation in HfO2/ TiN gate stacks. This paper relates the electrical properties to the chemical/physical properties of the high-epsiv dielectric and discusses test procedures specifically tailored to quantify gate stack reliability of HfO2/TiN gate stacks.

Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

Emerging Applications for High K Materials in VLSI Technology

This year marks a major materials milestone in the makeup of silicon-based fieldeffect transistors: in the microprocessors produced by leading manufacturers, the SiO 2 gate dielectric is being replaced by a hafnium-based dielectric. The incredible electronic properties of the SiO 2 /silicon interface are the reason that silicon has dominated the semiconductor industry and helped it grow to over $250 billion in annual sales, as reported by the Semicoriductor Industry Association (SIA), San Jose, CA. The shrinkage of transistor dimensions (Moore's law) has led to tremendous improvements in circuit speed and computer performance. At the same time, however, it has also led to exponential growth in the static power consumption of transistors due to quantum mechanical tunneling through an ever-thinner SiO 2 gate dielectric. This has spurred an intensive effort to find an alternative to SiO 2 with a higher dielectric constant (K) to temper this exploding power consumption. This article reviews the high-K materials revolution that is enabling Moore's law to continue beyond SiO 2 .

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S0883769400006333

Gate Oxides Beyond SiO2

The power consumption of capacitor leakage current, increase of the capacitor aspect ratio, and lack of higher dielectric constant (κ) material are the difficult challenges to downscaling dynamic random access memory (DRAM). This letter reports a new one-transistor ferroelectric-MOSFET (1T FeMOS) device that displays DRAM functions of a 5 ns switching time, 1012 on/off endurance cycles, and 30 times on/off retention windows at 5 s and 85 °C. A simple 1T process and a considerably low OFF-state leakage of 3×10-12 A/μm were achieved. This novel device was achieved by applying ferroelectric ZrHfO gate dielectric to a p-MOSFET, which is fully compatible with existing high-κ CMOS processing.

https://ir.nctu.edu.tw:443/bitstream/11536/23386/1/000329061300046.pdf

Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric

The analytical MOSFET intrinsic delay introduced in Part I of this paper is used to examine the tradeoffs between key device elements required in order for the performance scaling trend to continue in future high-performance CMOS generations. A scaling scenario based on contacted source/drain gate pitch is presented and used to examine the prospects of MOSFET performance in the future nodes. It is shown that, from 32-nm node onwards, MOSFET performance will counterscale, mainly due to increase in the parasitic gate capacitance as a result of proximity of the gate and source/drain electrodes. As a case study, the dependence of the transistor performance on various device parameters at the 32-nm node is analyzed. Reducing the fringing capacitance is shown to be the most effective approach to meet the required transistor delay.

MOSFET Performance Scaling—Part II: Future Directions

Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12A) for BE nFET devices to-date, consistent with simulations showing the need for ≪14A T inv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET's fabricated with gate-first high thermal budget processing with thin Tinv (≪13A) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET's into CMOS devices yielded large SRAM arrays.

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

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High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing