The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

Challenges for future semiconductor manufacturing

Multiple Gate Field Effect Transistors (MuGFET) with a fin pitch down to 50nm obtained with 193nm optical lithography and proposed fin quadrupling patterning method are demonstrated. The fins patterned with this technique feature improved CD control and line width roughness. High fin density in combination with Si-SEG that allows merging individual fins outside the spacer region lead to reduction in parasitic source/drain-resistance and 3-fold increase in drive current per surface unit.

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

The role of single wafer Rapid Thermal Processing (RTP) in semiconductor manufacturing has been steadily expanding over the last 2 decades. There are several reasons for the successful adaptation of this technology. These include more critical requirements by advanced semiconductor technologies with respect to thermal exposure and control, as well as tremendous improvements by the RTP equipment community in resolving some fundamental limitations of the tooling, historically restricting wide spread implementation. From rather humble beginnings, RTP technology has now established itself as indispensable to the production of advanced semiconductor products. We review the history and implementation of RTP technology in semiconductor processing technology at International Business Machines Corporation (IBM) from the late 1980s to recent time.

The Expanding Role of Rapid Thermal Processing in CMOS Manufacturing

The insatiable demand for digital information has led to the introduction and increasing adaptation of Silicon Photonics in digital communications to replace the much slower copper wires wherever possible. While most of today’s Silicon Photonics solutions are being manufactured using hybrid (no CMOS devices) integration, there is an increasing need to offer full integrated solutions (CMOS and Photonics) to improve system level performance and drive overall costs down. In this paper we’ll describe the challenges and innovative solutions used to develop and ultimately integrate a high performance Germanium (Ge) photodiode (PD) into a 90nm CMOS compatible process flow to provide a full monolithic Silicon Photonics solution.

Integrating a high performance Germanium photodiode into a CMOS compatible flow for a full monolithic Silicon Photonics solution

Off-state modulation of the floating-body potential in partially depleted silicon-on-insulator (PDSOI) transistors from the 90-nm technology generation is observed using pulsed current-voltage (I-V) measurements. Varying the off-value of the gate voltage is shown to either decrease the transient on-current (I/sub on,trans/) of PDSOI devices through gate-to-body leakage or increase I/sub on,trans/ due to gate-induced drain leakage. Dependence of I/sub on,trans/ on off-state gate bias is not observed in bulk devices, PDSOI devices with body contacts, or fully depleted SOI devices, confirming the role of floating-body in the observed effects. Thus, off-state conditions should be accounted for when considering floating-body effects and when using pulsed I-V measurements to study self-heating.

Off-state modulation of SOI floating-body

We present enhanced 90 nm node CMOS devices on a partially depleted SOI with 40 nm gate length, featuring advanced process modules for manufacture, including RSD (raised source/drain), disposable spacer, final spacer for S/D doping and silicide proximity, NiSi, and thermally optimized MOL (middle-of-line) process. For the first time, we systematically designed silicide proximity in SOI and post-activation thermal cycles to improve series resistance and gate activation. This paper demonstrates decoupled effects of the individual performance boosters on drive currents and minimization of dopant deactivation, which resulted in dramatic improvement of drive currents by 11% to 19% (820 /spl mu/A/um and 420 /spl mu/A/um at Ioff = 40 nA/um with Vdd = 1.0 V, for NFET and PFET, respectively), significant reduction in effective gate oxide thickness under gate inversion by /spl sim/1.2 /spl Aring/ and /spl sim/2.1 /spl Aring/, for NFET and PFET, respectively, and an excellent inverter delay of less than 5.4 ps at Lgate of 40 nm.

High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

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High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering