Content-addressable memory (CAM) and associative memory (AM) are types of storage structures that allow searching by content as opposed to searching by address. Such memory structures are used in diverse applications ranging from branch prediction in a processor to complex pattern recognition. In this paper, we review the emerging challenges and opportunities in implementing different varieties of CAM/AM structures. Beyond-CMOS silicon and nonsilicon memory technologies hold significant promise in implementing dense, fast, and energy-efficient CAM/AM structures. We describe circuit/architecture level implementations of CAM/AM using these technologies, as well as novel applications in different domains, including informatics, text analytics, data mining, and reconfigurable computing platforms.

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7- and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 〈110〉 channel orientation is more resilient to the MGG and LER variability in both architectures.

/pdf/finfet-versus-gate-all-around-nanowire-fet-performance-2wdmnm8wlp.pdf

FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Low latency and low implementation cost are two key requirements in NoCs. SMART routers implement multi-hop bypass, obtaining latency values close to an ideal point-to-point interconnect. However, it requires a significant amount of resources such as Virtual Channels (VCs), which are not used as efficiently as possible, preventing bypass in certain scenarios. This translates into increased area and delay, compared to an ideal implementation. In this paper, we introduce SMART++, an efficient multi-hop bypass mechanism which combines four key ideas: SMART bypass, multi-packet buffers, Non-Empty Buffer Bypass and Per-packet allocation. SMART++ relies on a more aggressive VC reallocation policy and supports bypass of buffers even when they are not completely free. With these desirable characteristics, SMART++ requires limited resources and exhibits high performance. SMART++ is evaluated using functional simulation and HDL synthesis tools. SMART++ without VCs and with a reduced amount of buffer slots outperforms the original SMART using 8 VCs, while reducing the amount of logic and dynamic power in an FPGA by 5.5x and 5.0x respectively. Additionally, it allows for up to 2.1x frequency; this might translate into more than 31.9% base latency reduction and 42.2% throughput increase.

SMART++: reducing cost and improving efficiency of multi-hop bypass in NoC routers

FinFET is the backbone device technology for CMOS electronics at deeply scaled technology nodes per Moore’s law. Recently, the FinFET concept has been leveraged to develop a new generation of vertical power transistors based on wide-bandgap (WBG) and ultrawide-bandgap (UWBG) semiconductors for kilovolts and high-power applications. The sidewall gate-stack in a vertical power FinFET can rely on either a metal–oxide–semiconductor (MOS) structure or a p-n junction, rendering a Fin-MOSFET or a fin-based junction field-effect transistor (Fin-JFET), respectively. Although the device technologies are still at the early stage of development, 1.2-kV-class WBG gallium nitride (GaN) power Fin-MOSFETs have demonstrated one of the highest static and switching performances in all similarly rated power transistors; UWBG gallium oxide power Fin-MOSFETs have shown high performance up to a breakdown voltage over 2.6 kV. Early UWBG diamond lateral power Fin-MOSFETs have also been demonstrated. Meanwhile, GaN power Fin-JFETs are currently under active development. This article provides a comprehensive tutorial and review of the background and recent advances in WBG and UWBG vertical power FinFETs. It covers fundamental device physics, device and process development, as well as the static and switching performance of various power Fin-MOSFETs and Fin-JFETs. This article is concluded by identifying the current challenges and exciting research opportunities in this very dynamic research field.

(Ultra)Wide-Bandgap Vertical Power FinFETs

Gallium nitride (GaN) is becoming a mainstream semiconductor for power and radio-frequency (RF) applications. While commercial GaN devices are increasingly being adopted in data centers, electric vehicles, consumer electronics, telecom and defense applications, their performance is still far from the intrinsic GaN limit. In the last few years, the fin field-effect transistor (FinFET) and trigate architectures have been leveraged to develop a new generation of GaN power and RF devices, which have continuously advanced the state-of-the-art in the area of microwave and power electronics. Very different from Si digital FinFET devices, GaN FinFETs have allowed for numerous structural innovations based on engineering the two-dimensional-electron gas or p–n junctions, in both lateral and vertical architectures. The superior gate controllability in these fin-based GaN devices has not only allowed higher current on/off ratio, steeper threshold swing, and suppression of short-channel effects, but also enhancement-mode operation, on-resistance reduction, current collapse alleviation, linearity improvement, higher operating frequency, and enhanced thermal management. Several GaN FinFET and trigate device technologies are close to commercialization. This review paper presents a global overview of the reported GaN FinFET and trigate device technologies for RF and power applications, as well as provides in-depth analyses correlating device design parameters to device performance space. The paper concludes with a summary of current challenges and exciting research opportunities in this very dynamic research field.

https://iopscience.iop.org/article/10.1088/1361-6641/abde17/pdf

GaN FinFETs and trigate devices for power and RF applications: review and perspective

Since Moore’s law driven scaling of planar MOSFETs
faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing
to the presence of multiple (two/three) gates, FinFETs/Trigate
FETs are able to tackle short-channel effects (SCEs) better than
conventional planar MOSFETs at deeply scaled technology nodes
and thus enable continued transistor scaling. In this paper, we
review research on FinFETs from the bottommost device level
to the topmost architecture level. We survey different types of
FinFETs, various possible FinFET asymmetries and their impact,
and novel logic-level and architecture-level tradeoffs offered by
FinFETs. We also review analysis and optimization tools that
are available for characterizing FinFET devices, circuits, and
architectures.

/pdf/finfets-from-devices-to-architectures-3wvjf3zgcz.pdf

FinFETs: From Devices to Architectures

FinFETs have begun replacing planar CMOS in the post-22 nm era because of their superior short-channel behavior. Though FinFETs will continue to extend Moore's law for the next few technology generations, 3-D vertical integration will enable more-than-Moore density increase by increasing the transistor count that can be accommodated in an IC package. Compared to conventional through-silicon-via (TSV)-based 3-D integration methods, monolithic 3-D integration enables higher density of transistors owing to the much smaller monolithic inter-tier vias (MIVs). In this paper, for the first time, we explore the design possibilities for FinFET-based ultra-high density monolithic 3-D SRAMs. These SRAMs can exploit the height difference between the n- and p-FinFETs placed in two different layers to improve overall SRAM stability. We investigate several 6T and 8T monolithic 3-D FinFET SRAM bitcells and evaluate their dc and transient stability/performance metrics, taking process variations into account. We propose a new 8T 3-D SRAM bitcell that shows a 39% improvement in read stability and 25% improvement in footprint area without affecting writeability, when compared with the conventional 2-D 6T SRAM bitcell.

Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read Stability

Several small lensoidal bodies of felsic volcanics are exposed in a curvilinear pattern within the brecciated granitoids of Bundelkhand Gneissic Complex (BGC) at Mohar. Sub-surface data reveals extensive presence of these felsic volcanics below the sediment of Vindhyan Supergroup. It occurs like a sheet with thickness varying from 12 m to 134 m. Its lateral extent has been traced upto 4.8 km. Multiple flows of felsic magma are identified based on colour, granularity, cross cutting relations and cyclic distribution of multiple vesicular bands along the entire thickness of felsic magma. The felsic rock contains upto 13.21% K2O. Chemical composition of these felsic volcanics varies across the column. Petrographically and chemically all these felsic volcanics are identified as rhyolite or rhyolite tuff.

Uranium mineralisation associated with felsic volcanism at Mohar, Shivpuri district, Madhya Pradesh

Rb-Sr isotopic data for the Tamparkola granite, northwest of Bonaigarh, and Bamra granite, southeast of Barnra, Sundergarh district, Orissa have yielded similar ages of 2746&#177144 Ma and 2738±28 Ma, respectively. Small granite exposures intruding the Iron Ore Group in the southern part of Tamparkola granite, have also indicated similar Whole Rock Rb-Sr age of 2867&#17786 Ma. These may be correlated with the Bonai granite. Significant crustal component was involved in the generation of these granites, as indicated by high initial Sr ratio, and their emplacement probably marks a major terminal cratonisation event in northwestern part of the Singhbhum-North Orissa Craton. Ths study does not support the view that the Tamparkola Granite is equivalent to the Itrna/Ekma granites that are intrusive into the Gangpur Group. These age results call for a revision of the stratigraphy of the Bonai-Gangpur tract, in that the Darjing Group unconformably overlies both the Bonai granite and Tamparkola granite, with the Mesoproterozoic Kunjar sedimentary sequence representing the youngest of the regional succession.

Geochronology of the Granitoids of the Kunjar Area, Sundergarh District, Orissa: Implications to the Regional Stratigraphy

With the increasing number of components in multiprocessor systems-on-chip, standard bus based communication architectures face a formidable scalability challenge Network-on-chip (NoC), a type of communication architecture, addresses this scalability problem by distributing the communication resources among the communicating components A huge bottleneck to modern NoC design is its extremely slow simulation/prototyping phase Traditionally, analytical performance models have been used to speed up this phase However, the currently available analytical models are not applicable to state-of-the-art NoCs This forces NoC designers to rely on simulation/prototyping In this work, we propose an analytical NoC performance analysis methodology for modeling the state-of-the-art single-cycle multi-hop asynchronous repeated traversal (SMART) NoC that enables packets to partially or completely bypass routers from source to destination To the best of our knowledge, this is the first work on analytical modeling of NoCs that enable bypassing of routers Our method registers a prediction error in network latency that is as low as 1 percent, and on an average below 25 and 84 percent, respectively, compared with the cycle-accurate GARNET network simulator and the gem5 full-system simulator running the PARSEC benchmark suite The method also leads to two orders of magnitude speedup in computation time It can account for variations in NoC design parameters, such as the maximum number of hops per cycle, number of virtual channels, flit size, buffer depth per virtual channel, etc Even when these NoC design parameters are varied, our method's results remain within 5 percent of GARNET's results

Analytical Modeling of the SMART NoC

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