This paper provides evidence that, as a result of constant-field scaling, the peak fT (approx. 0.3 mA/mum), peak fMAX (approx. 0.2 mA/mum), and optimum noise figure NFMIN (approx. 0.15 mA/mum) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers

The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks

We have experimentally studied the suitability of nanometer-scale In0.7Ga0.3As high-electron mobility transistors (HEMTs) as an n-channel device for a future high-speed and low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50- to 150-nm gate-length In0.7Ga0.3As HEMTs with different gate stack designs. This has allowed us to investigate the role of Schottky barrier height (PhiB) and insulator thickness (tins) on the logic characteristics of In0.7Ga0.3As HEMTs. The best 50-nm HEMTs with the highest PhiB and the smallest tins exhibit an ION/IOFF ratio in excess of 104 and a subthreshold slope (S) below 86 mV/dec. These nonoptimized 50-nm In0.7Ga0.3As HEMTs also show a logic gate delay (CV/I) of around 1 ps at a supply voltage of 0.5 V, while maintaining an ION/IOFF ratio above 104, which is comparable to state-of-the-art Si MOSFETs. As one of the alternatives for beyond-CMOS technologies, we believe that InAs-rich InGaAs HEMTs hold a considerable promise.

Logic Suitability of 50-nm $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ HEMTs for Beyond-CMOS Applications

We describe a prospective strategy for reading the encyclopedic information encoded in the genome: using a nanopore in a membrane formed from a metal-oxide semiconductor (MOS)-capacitor to sense the charge in deoxyribonucleic acid (DNA). In principle, as DNA permeates the capacitor-membrane through the pore, the electrostatic charge distribution characteristic of the molecule should polarize the capacitor and induce a voltage on the electrodes that can be measured. Silicon nanofabrication and molecular dynamic simulations with atomic detail are technological linchpins in the development of this detector. The sub-nanometer precision available through silicon nanotechnology facilitates the fabrication of the detector, and molecular dynamics provides us with a means to design it and analyze the experimental outcomes.

Beyond the gene chip

A 45-Gb/s BiCMOS decision circuit operating from a 2.5-V supply is reported. The full-rate retiming flip-flop operates from the lowest supply voltage of any silicon-based flip-flop demonstrated to date at this speed. MOS and SiGe heterojunction-bipolar-transistor (HBT) current-mode logic families are compared. Capitalizing on the best features of both families, a true BiCMOS logic topology is presented that allows for operation from lower supply voltages than pure HBT implementations without compromising speed. The topology, based on a BiCMOS cascode, can also be applied to a number of millimeter-wave (mm-wave) circuits. In addition to the retiming flip-flop, the decision circuit includes a broadband transimpedance preamplifier to improve sensitivity, a tuned 45-GHz clock buffer, and a 50-/spl Omega/ output driver. The first mm-wave transformer is employed along the clock path to perform single-ended-to-differential conversion. The entire circuit, which is implemented in a production 130-nm BiCMOS process with 150-GHz f/sub T/ SiGe HBT, consumes 288 mW from a 2.5-V supply, including only 58 mW from the flip-flop.

/pdf/a-2-5-v-45-gb-s-decision-circuit-using-sige-bicmos-logic-24xt7nnn82.pdf

A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic

The performance capabilities of InP-based pnp heterojunction bipolar transistors (HBT's) have been investigated using a drift-diffusion transport model based on a commercial numerical simulator. The low hole mobility in the base is found to limit the current gain and the base transit time, which limits the device's cutoff frequency. The high electron majority carrier mobility in the n/sup +/ InGaAs base allows a reduction in the base doping and width while maintaining an adequately low base resistance. As a result, high current gain (>300) and power gain (>40 dB) are found to be possible at microwave frequencies. A cutoff frequency as high as 23 GHz and a maximum frequency of oscillation as high as 34 GHz are found to be possible without base grading. Comparison is made with the available, reported experimental results and good agreement is found. The analysis indicates that high-performance pnp InP-based HBT's are feasible, but that optimization of the transistor's multilayer structure is different than for the npn device.

Simulation and design of InAlAs/InGaAs pnp heterojunction bipolar transistors

RF CMOS performance from a 90nm derivative communications process technology is compared to SiGe BJT performance. NMOS performance at f/sub T//f/sub max/ = 209/248 GHz (70nm) and f/sub T//f/sub max/ = 166/277 GHz (80nm) with F/sub min/ at 0.3 dB (2GHz) and 0.6 dB (10GHz) suggests there is no major reason to implement SiGe HBTs BiCMOS in an integrated communications process.

A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications

Predictive compact models have been developed to describe NQS effects and thermal noise in Intel's 90nm radio-frequency (RF) CMOS (Kuhn, et al., 2002). The physical approach enables modeling transistor performance from DC to RF with one single set of parameters. Quantum correction on classical induced-gate-noise model is observed for the first time in ultra-thin oxide technology.

Predictive compact modeling of NQS effects and thermal noise in 90nm mixed-signal/RF CMOS technology

This work describes the noise figure performance of CMOS transistors at the 90 nm technology node. Noise parameters are measured from 2-18 GHz, resulting in a minimum noise figure less than 2 dB across the range of measured frequencies for both NMOS and PMOS. Data is presented showing the effect of total gate width, gate length, and bias on the noise parameters.

http://ieeexplore.ieee.org/iel5/9277/29468/01335785.pdf

Noise performance of 90 nm CMOS technology

We show that the minimization of device R/sub n/ allows us to simultaneously approach noise and input match in CMOS LNA designs in a topology independent fashion The dependence of R/sub n/ on designer specifiable parameters is derived using a theoretical analysis of long channel (ie square-law) devices Experimental results are shown to confirm this dependence for short-channel devices Using experimental data from a 018 /spl mu/m technology, we show that a low R/sub n/ design results in a /spl ges/2/spl times/ increase in the bandwidth over which an optimal noise figure can be obtained The desensitization of the device with a low R/sub n/ provides a greater immunity to impedance mismatches, modeling errors and manufacturing variations

Desensitized design of MOS low noise amplifiers by R/sub n/ minimization

It can be shown that devices with low noise resistance (R/sub n/) values can significantly relax the noise-input match trade-off in LNA design, resulting in desensitized wideband LNAs. In this paper, we show that the measurements of such devices are error-prone and can cause modeling and simulation inaccuracies. Using a CAD-oriented approach, an error-propagation analysis from measurements to a device-model is performed. We find that the errors in measurements affect the simulated values of R/sub n/, NF/sub min/ and B/sub opt/ the least and these parameters need to be calibrated well in any good device model. Values of G/sub opt/ are shown to propagate from measurements and errors are bigger for devices with a large transadmittance (/sub y21/). We suggest the use of scaled MOS models extracted from devices with high R/sub n/ to predict the values of G/sub opt/ for devices with low R/sub n/, using the other noise parameters as calibration points.

Measurement and modeling of noise parameters for desensitized low noise amplifiers

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