Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks

To accurately model 4H-SiC MOSFETs over a wide temperature operating range, this work proposes a compact modeling method based on physically informed artificial neural networks(ANNs). The method relies on two separate ANNs, the first ANN is based on the symmetry-modified BSIM model, which is used to predict the main trends of the I-V curves. The second ANN is used to train a model correction function related to non-ideal factors not covered in the above model. This method is able to ensure the symmetry requirements of the model even without adding a smoothing function. The introduction of physical information allows the model to accurately predict the I-V characteristics of the MOSFET and guarantee the smoothness of its derivatives. A major advantage is that less than 30% of the data is needed to achieve the same model accuracy as ANN without physical information. We have simulated the designed device models in Spice software for E/E saturated load NMOS inverters and NAND logic circuits, and the results show that the maximum model error does not exceed 1.8%.

A Physics-Informed Artificial Neural Network Modeling Approach for Wide Temperature Range 4H-SiC MOSFETs

Integrated Circuits (ICs) are the target of diverse attacks during their lifetime. Fabrication-time attacks, such as the insertion of Hardware Trojans, can give an adversary access to privileged data and/or the means to corrupt the IC's internal computation. Post-fabrication attacks, where the end-user takes a malicious role, also attempt to obtain privileged information through means such as fault injection and probing. Taking these threats into account and at the same time, this paper proposes a methodology for Security-Aware Layout Synthesis (SALSy), such that ICs can be designed with security in mind in the same manner as power-performance-area (PPA) metrics are considered today, a concept known as security closure. Furthermore, the trade-offs between PPA and security are considered and a chip is fabricated in a 65nm CMOS commercial technology for validation purposes - a feature not seen in previous research on security closure. Measurements on the fabricated ICs indicate that SALSy promotes a modest increase in power in order to achieve significantly improved security metrics. 

pdf/salsy-security-aware-layout-synthesis-4i4uztcy25.pdf

SALSy: Security-Aware Layout Synthesis

Ternary logic is popular where it uses logic levels of 0, 1 and 2 instead of using the old binary logic structure. Due to this, it has grown to be very popular method in many applications. It is used in applications which focuses on high density data processing and also to obtain lower power consumption. The design of this SRAMs poses lot of challenges and there is a high demand for robust and optimized memory units. This work concentrates on overcoming the problems of higher power consumption that is found in traditional SRAM cells. It focusses on the comprehensive study if 6T, 8T and 10T SRAM cells. Through this study, the performance metrics are analyzed for power consumption and R/W efficiency. The results obtained shows the lower consumption of power and improved R/W efficiency.

Ternary SRAM Cell Designs for Next-Generation: A Comprehensive Investigation of 6T, 8T, and 10T Designs

Due to cost benefits, supply chains of integrated circuits (ICs) are largely outsourced nowadays. However, passing ICs through various third-party providers gives rise to many security threats, like piracy of IC intellectual property or insertion of hardware Trojans, i.e., malicious circuit modifications. In this work, we proactively and systematically protect the physical layouts of ICs against post-design insertion of Trojans. Toward that end, we propose TroLLoc, a novel scheme for IC security closure that employs, for the first time, logic locking and layout hardening in unison. TroLLoc is fully integrated into a commercial-grade design flow, and TroLLoc is shown to be effective, efficient, and robust. Our work provides in-depth layout and security analysis considering the challenging benchmarks of the ISPD'22/23 contests for security closure. We show that TroLLoc successfully renders layouts resilient, with reasonable overheads, against (i) general prospects for Trojan insertion as in the ISPD'22 contest, (ii) actual Trojan insertion as in the ISPD'23 contest, and (iii) potential second-order attacks where adversaries would first (i.e., before Trojan insertion) try to bypass the locking defense, e.g., using advanced machine learning attacks. Finally, we release all our artifacts for independent verification [2]. 

pdf/trolloc-logic-locking-and-layout-hardening-for-ic-security-1xg9tib3m9.pdf

TroLLoc: Logic Locking and Layout Hardening for IC Security Closure
  against Hardware Trojans

Hardware security is emerging in the very large scale integration (VLSI). The seminal threats, like hardware Trojan insertion, probing attacks, and fault injection, are hard to detect and almost impossi-ble to fix at post-design stage. The optimal solution is to prevent them at the physical design stage. Usually, defending against them may cause a lot of power, performance, and area (PPA) loss. In this paper, we propose a PPA-friendly physical layout security closure framework ASSURER. Reward-directed placement refinement and multi-threshold partition algorithm are proposed to assure Trojan threats are empty. Cleaning up probing attacks is established on a patch-based ECO routing flow. Evaluated on the ISPD'22 bench-marks, ASSURER can clean out the Trojan threat with no leakage power increase when shrinking the physical layout area. When not shrinking, ASSURER only increases 14% total power. Compared with the work of first place in the ISPD2022 Contest, ASSURE reduced 53% additional total power consumption, and probing vulnerability can be reduced by 97.6% under the premise of timing closure. We believe this work shall open up a new perspective for preventing Trojan insertion and probing attacks.

ASSURER: A PPA-friendly Security Closure Framework for Physical Design

With the rapid development of semiconductor technology, traditional equation-based modeling faces challenges in accuracy and development time. To overcome these limitations, neural network (NN)-based modeling methods have been proposed. However, the NN-based compact model encounters two major issues. Firstly, it exhibits unphysical behaviors such as un-smoothness and non-monotonicity, which hinder its practical use. Secondly, finding an appropriate NN structure with high accuracy requires expertise and is time-consuming. In this paper, we propose an Automatic Physical-Informed Neural Network (AutoPINN) generation framework to solve these challenges. The framework consists of two parts: the Physics-Informed Neural Network (PINN) and the two-step Automatic Neural Network (AutoNN). The PINN is introduced to resolve unphysical issues by incorporating physical information. The AutoNN assists the PINN in automatically determining an optimal structure without human involvement. We evaluate the proposed AutoPINN framework on the gate-all-around transistor device. The results demonstrate that AutoPINN achieves an error of less than 0.05%. The generalization of our NN is promising, as validated by the test error and the loss landscape. The results demonstrate smoothness in high-order derivatives, and the monotonicity can be well-preserved. We believe that this work has the potential to accelerate the development and simulation process of emerging devices.

/pdf/a-physics-informed-automatic-neural-network-generation-2hnejq5q.pdf

A Physics-Informed Automatic Neural Network Generation Framework for Emerging Device Modeling

With the CMOS technology downscaling to the deep nanoscale, the aging effects of devices degrade circuit performance and even lead to functional failure. The stress analysis is critical to evaluate the influence of aging effects on digital circuits. Some related analytical work has recently focused on reliability-aware circuit analysis. Nevertheless, the aging dependence among different devices is not considered, which will induce errors of degradation evaluation in the digital circuit. In order to improve the accuracy of reliability-aware static timing analysis, an improved analytical method is proposed by employing logical resolving. Experimental results show that the proposed method has a better evaluation accuracy of aging path delay than traditional strategies. For aging timing evaluation on aging paths, excessive pessimism can be reduced by employing the proposed method. And, a 378× speedup is achieved while having a 0.56% relative error compared with precise SPICE simulation. Moreover, the circuit performance sacrifice of an aging-aware synthesis flow with the proposed method can be decreased. Due to the high efficiency and high accuracy, the proposed method can meet the speed demands of large-scale digital circuit reliability analysis while achieving transistor simulation accuracy.

Logical Resolving-Based Methodology for Efficient Reliability Analysis

In this paper, we investigate the effects of negative bias instability (NBTI) and self-heating effect (SHE) on threshold voltage in NSFETs. To explore accurately the interaction between SHE and NBTI, we established an NBTI simulation framework based on trap microdynamics and considered the influence of the self-heating effect. The results show that NBTI weakens the SHE effect, while SHE exacerbates the NBTI effect. Since the width of the nanosheet in NSFET has a significant control effect on the electric field distribution, we also studied the effect of the width of the nanosheet on the NBTI and self-heating effect. The results show that increasing the width of the nanosheet will reduce the NBTI effect but will enhance the SHE effect. In addition, we extended our research to the SRAM cell circuit, and the results show that the NBTI effect will reduce the static noise margin (SNM) of the SRAM cell, and the NBTI effect affected by self-heating will make the SNM decrease more significantly. In addition, our research results also indicate that increasing the nanosheet width can help slow down the NBTI effect and the negative impact of NBTI on SRAM performance affected by the self-heating effect.

Interaction of Negative Bias Instability and Self-Heating Effect on Threshold Voltage and SRAM (Static Random-Access Memory) Stability of Nanosheet Field-Effect Transistors

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