The IEEE T RANSACTIONS ON C OMPUTER -A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS publishes manuscripts focusing on methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, veriﬁcation, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.TheIEEE T RANSACTIONS ON C OMPUTER -A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS is published by the IEEE Council on Electronic Design Au- tomation. The IEEE Council on Electronic Design Automation (CEDA) is an organizational unit of the IEEE that has six IEEE member societies, namely, Antennas and Propagation, Circuits and Systems, Computer, Electron Devices, Microwave Theory and Techniques, and the Solid-State Circuits Societies. The objectives of CEDA include fostering design automation of electronic circuits and systems at all levels, by means of publications, conferences/workshops and volunteer activities. For membership and subscription information and pricing, please visit www.ieee.org/membership-catalog. Member copies of Transactions/Journals are for personal use only.

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

The invention discloses a simulation program with integrated circuit emphasis (SPICE) model building method for a size reduced process, which comprises the following steps of: step 1, extracting a Berkeley shortchannel igfet model (BSIM) according to the size of a metal oxide semiconductor (MOS) apparatus after the MOS apparatus is reduced in size practically; step 2, correcting a simulation netlist by adding an option function of an SCALE parameter in a circuit emulator and making the SCALE parameter equal to a size reducing factor of a size reducing process; and step 3, correcting an XL model parameter and an XW model parameter of the BSIM, wherein XL is equal to OFFSETL and XW is equal to OFFSETW. A chip agent processing factory does not need to develop a new circuit design environment, so the corresponding technical development cost can be saved. A practical apparatus based on the size reduced process and a circuit performance can be convenient to realize effectively in a way that a circuit designer directly simulates the design of an original circuit which is not reduced in size, so the simulation efficiency can be improved.

Simulation program with integrated circuit emphasis (SPICE) model building method for size reduced process

DVFS (dynamic voltage and frequency scaling) is a system-level technique that adjusts voltage and frequency levels of CPU/GPU at runtime to balance energy efficiency and high performance. DVFS has been studied for many years, but it is considered still challenging to realize a DVFS that performs ideally for mobile devices for two main reasons: i) an optimal power budget distribution between CPU and GPU in a power-constrained platform can only be defined by the application performance, but conventional DVFS implementations are mostly application-agnostic; ii) mobile platforms experience dynamic thermal environments for many reasons such as mobility and holding methods, but conventional implementations are not adaptive enough to such environmental changes. In this work, we propose a deep reinforcement learning-based frequency scaling technique, zTT. zTT learns thermal environmental characteristics and jointly scales CPU and GPU frequencies to maximize the application performance in an energy-efficient manner while achieving zero thermal throttling. Our evaluations for zTT implemented on Google Pixel 3a and NVIDIA JETSON TX2 platform with various applications show that zTT can adapt quickly to changing thermal environments, consistently resulting in high application performance with energy efficiency. In a high-temperature environment where a rendering application with the default mobile DVFS fails to keep producing more than a target frame rate, zTT successfully manages to do so even with 23.9% less average power consumption.

zTT: learning-based DVFS with zero thermal throttling for mobile devices

Wake-up circuits in smart microsystems make huge contributions to energy conservation of electronic networks in unmanned areas, which still require higher pressure-triggering sensitivity and lower power consumption. In this work, a bionic triboelectric nanogenerator (bTENG) is developed to serve as a self-powered motion sensor in the wake-up circuit, which captures slight mechanical disturbances and overcomes the drawback of conventional self-powered motion sensors in the wake-up circuit that the circuit can only be triggered when a considerable pressure is applied on the sensor. The bTENG mimics the structure of plants and the addition of the leaf-shaped tentacle structures can increase the electrical outputs by four times, which largely extends the detection range of the wake-up circuit. The bTENG can detect both noncontact and contact mechanical disturbances; and voltages generated from both situations can trigger the wake-up system. Moreover, the specially designed circuit that is compatible with the bTENG can help more accurately control the wake-up system and prolong the battery life of the electronic networks to 12.4 times. An intrusion detection system is established in the wake-up circuit to distinguish human motion and judge the scene. This work opens new horizons for wake-up technologies, and provides new routes for persistent sensing.

https://onlinelibrary.wiley.com/doi/pdf/10.1002/advs.202000254

Ultralow Quiescent Power-Consumption Wake-Up Technology Based on the Bionic Triboelectric Nanogenerator.

A new bipolar transistor model called VBIC has recently been developed and is likely to replace the Gummel-Poon model as the new industry standard bipolar transistor model. This paper focuses on the comparison of the VBIC and Gummel-Poon models under the DC operations. The extraction and optimization procedure coded in S+ statistical language and required for VBIC simulation is also developed and presented.

/pdf/comparison-of-the-new-vbic-and-conventional-gummel-poon-1tjunnrer0.pdf

Comparison of the new VBIC and conventional Gummel-Poon bipolar transistor models

This paper presents criteria, using simple integer arithmetic, to determine if a layout of a pair of devices broken into multiple, identical sections cancels the effect of nonlinear process gradients. These criteria allow quantification of 12 layout symmetries that can be leveraged to cancel specific process gradient components. “Dispersion,” the degree to which device segments are distributed throughout a layout, is also quantified in a simple and intuitive way, and used to identify which of multiple gradient canceling layouts is best. Techniques to construct maximally dispersive quadratic gradient canceling layouts with arbitrary numbers of rows and columns are presented.

Layout Symmetries: Quantification and Application to Cancel Nonlinear Process Gradients

This article presents PSPHV, a surface-potential-based compact model for laterally diffused MOS (LDMOS) transistors. PSPHV includes a new drain voltage scaling technique that enables accurate modeling of saturation in transistors with nonuniform lateral doping; gate bias-dependent interface charge, which models the gradual channel turn- ON seen in devices with halo doping; internal drain bias clamping, which eliminates the capacitance spikes seen in most existing LDMOS models; and a new avalanche current model for the drift region that accounts for the Kirk effect. PSPHV models the drain expansion effect and diode reverse recovery and is verified against experimental data.

PSPHV: A Surface-Potential-Based Model for LDMOS Transistors

This paper provides an industry perspective on the present state of compact models for MOS transistors. It highlights the complexity of layout-dependent effects in modern transistors, reviews some common misunderstandings of MOS transistor capacitances, and introduces a new, structurally symmetric, “gate-as-input” equivalent network for these capacitances. Areas of focus for the future model developments are also proposed.

Compact Models for MOS Transistors: Successes and Challenges

This paper presents the details of JFETIDG, a compact model for independent dual-gate junction field-effect transistors with any combination of p-n junction or MOS gates. JFETIDG accounts for nonlinearity from depletion pinching, velocity saturation, and self-heating, and includes extensive modeling of geometry and temperature dependences, parasitics, noise, and statistical variations. We also demonstrate that it accurately models long channel junctionless MOS transistors. The model is verified by comparison with TCAD simulations and experimental data. Verilog-A code for JFETIDG is available in the public domain.

JFETIDG: A Compact Model for Independent Dual-Gate JFETs With Junction or MOS Gates

This paper studies the phase diagram of source pinchoff of dual-gate JFETs and presents a source pinchoff modeling formalism that is smooth across the phase boundaries. Based on this, an $I_{\textrm {ds}}$ model is derived, which is numerically robust for any value of top- and bottom-gate voltages. The method is applied to both the exact model for $I_{\textrm {ds}}$ and an approximated form based on mid-point-potential linearization, and is verified by comparison with numerical simulation. Modeling of short-channel effects is included.

Dual-Gate JFET Modeling II: Source Pinchoff Voltage and Complete $I_{\textrm {ds}}$ Modeling Formalism

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