A new superjunction LDMOS (SJ-LDMOS) is proposed with the step doping buffered layer under the SJ layer to obtain the low loss for the high-voltage region. The substrate-assisted depletion effect, which results from the p-type substrate for the n-channel SJ-LDMOS, has been eliminated by the step doping buffer layer. By the effect of the electric field modulation, a more uniform lateral electric filed is obtained due to the new high-electric field peaks introduced by the buffered step doping, which improves the breakdown voltage (BV) and average lateral electric field. Using ISE simulation, the BV of proposed SJ-LDMOST is increased by $\sim 50$ % than that of the conventional LDMOS, and improved by $\sim 32$ % than that of buffered SJ-LDMOS. The lateral average electric field is increased to 19 V/ $\mu $ m in the high-voltage region The experimental ${R} _{\mathbf {\mathrm{{\scriptstyle ON}},{\textrm sp}}}$ of the proposed SJ-LDMOS is 241 m $\Omega \,\cdot $ $\mathrm{cm}^{\mathrm {\mathbf {2}}}$ with a BV of 368 V, breaking the silicon limit relationship for ${R} _{\mathrm{{\scriptstyle ON}},\textrm {sp}}$ of 71.8 m $\Omega ~\cdot ~\mathrm{cm}^{\mathrm {\mathbf {2}}}$ with the BV of 242 V in the conventional LDMOS with the same drift region length The merit of BV/ $R _{\mathrm{{\scriptstyle ON}},\textrm {sp}}$ is 15.3 for the proposed SJ-LDMOS compared with that of 3.4 for the conventional LDMOS.

New Superjunction LDMOS Breaking Silicon Limit by Electric Field Modulation of Buffered Step Doping

A junction-isolated triple RESURF (JITR) LDMOS with high breakdown voltage (BV) and low specific on-resistance (R
 on,sp
) is proposed in this letter. Compared with the conventional triple RESURF (CTR) LDMOS, the new structure features a highly doped n-type top (N-top) layer at the surface of N-well, providing a low on-resistance surface conduction path in the on-state. The experimental result demonstrates that low R
 on,sp
 and high BV of above 730 V are achieved by the JITR LDMOS. R
 on,sp
 of the JITR LDMOS is about 15%-24.3% lower than that of the CTR LDMOS. The JITR LDMOS with horizontal N-top layer and P-buried layer resembles a super junction (SJ) LDMOS. Compared with the reported SJ LDMOS, the SJ layer of JITR LDMOS is formed in the longitudinal direction instead of the width direction, and the proposed JITR LDMOS exhibits almost the highest BV and high power figure of merit (FOM, defined as BV
 2
/R
 on,sp
) in comparison to the published SJ LDMOS.

A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

Lateral DMOS transistors are widely used in mixed-signal integrated-circuit design as integrated high-voltage switches and drivers. The LDMOS with shallow-trench isolation (STI) is the device of choice to achieve voltage and current capability integrated in the basic CMOS processes. In this review, the electrical characteristics of the STI-based LDMOS transistors are investigated over an extended range of operating conditions through experiments and numerical analysis. The LDMOS high electric-field characteristics are explained to the purpose of investigating the effects on reliability and device performance under hot-carrier stress (HCS) conditions. A review of the HCS modeling is addressed to provide an understanding of the degradation kinetics and mechanisms. TCAD simulations of the degradation are finally proposed to explain the HCS effects on a wide range of biases and temperatures, confirming the experimental results.

Characterization and modeling of electrical stress degradation in STI-based integrated power devices

Advanced 0.16 μm BCD technology platform offering dense logic transistors (1.8 V-5 V CMOS) and high performance analog features has been developed. Thanks to dedicated field plate optimization, body and drain engineering, state of the art power devices (8 V to 42 V rated) have been obtained ensuring large Safe Operating Areas with best RONXAREA-BVDSS tradeoff.

BCD8sP: An advanced 0.16 μm technology platform with state of the art power devices

A novel superjunction (SJ) lateral double-diffused MOSFET (LDMOS) with a deep High- K (HK) dielectric trench (HK SJ-LDMOS) is proposed and its mechanism is investigated by Technology Computer Aided Design (TCAD) simulations. The HK dielectric trench is embedded under the n+ drain, which is connected with the drain electrode. In the OFF-state, the reshaping effect of HK trench enhances the bulk electric field strength and weakens the peak electric field around the edge of the drain diffusion, which increases the breakdown voltage (BV). Moreover, because of the assistant depletion effect by the HK trench, a lower resistivity substrate is allowed for HK SJ-LDMOS, which also increases the doping concentration of the n-type buffer layer under the SJ layer of HK SJ-LDMOS, correspondingly. Thus, a lower specific ON-resistance ( ${R}_{ \mathrm{ ON},\text {sp}}$ ) is also obtained. Simulation results show that the BV increases by 35.2% in comparison with the conventional buffered SJ-LDMOS with the same drift length. Moreover, HK SJ-LDMOS presents an excellent figure of merit, which is two times higher than that of the conventional buffered SJ-LDMOS.

Novel Superjunction LDMOS With a High- K Dielectric Trench by TCAD Simulation Study

We present a new BCD technology in a 0.18 μm technology platforms with a capability of 7 to 60V high-voltage devices such as DEMOS and LDMOS. The developed 0.18 mum BCD process provides various kinds of high voltage LDMOS such as 7, 12, 20, 50, 60 V LDMOS transistors for variety of applications. The power LDMOS transistors in the process have very competitive specific on-resistance compared to previous results.

BD180 - a new 0.18 μm BCD (Bipolar-CMOS-DMOS) Technology from 7V to 60V

We experimentally demonstrate a Super-Junction LDMOS transistor in a 0.18 µm BCD technology. The buffered Super-Junction structure is implemented by the use of existing N- and P-drift layer, which are optimized for conventional 20V to 30V LDMOS transistors. The breakdown voltage and the specific on-resistance of the fabricated Super-Junction LDMOS are 98.6 V and 1.01 mΩ⋅cm2, respectively. The TLP measurement results show fairly good electrical SOA characteristics up to 78V for all gate voltages.

Implementation of buffered Super-Junction LDMOS in a 0.18um BCD process

0.18μm BCD technology with the best-in-class nLDMOS is presented. The drift of nLDMOS is optimized to ensure lowest Rsp by using multi-implants and appropriate thermal recipe. The optimized 24V nLDMOS has BV DSS =36V and Rsp=14.5 mΩ-mm2. Electrical SOA and long-term hot electron (HE) SOA are also evaluated. The maximum operating voltage less than 10% degradation of on-resistance is 24.4V.

BD180LV - 0.18 μm BCD technology with best-in-class LDMOS from 7V to 30V

A versatile 30V analog CMOS process in a 0.18 μm technology node has been developed by using cost-effective and modular fashion. To reduce the thermal budget deep NWELL isolation is formed after CMOS well formation. The drain-extended (DE) CMOS from 7V to 30V shows very competitive trade-off performance between the breakdown voltage and the specific on-resistance. In addition, low 1/f noise of 5V CMOS can be obtained by pure gate oxide process.

A versatile 30V analog CMOS process in a 0.18μm technology for power management application

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Papers

BD180 - a new 0.18 μm BCD (Bipolar-CMOS-DMOS) Technology from 7V to 60V

Implementation of buffered Super-Junction LDMOS in a 0.18um BCD process

BD180LV - 0.18 μm BCD technology with best-in-class LDMOS from 7V to 30V

A versatile 30V analog CMOS process in a 0.18μm technology for power management application