Dynamic verification is widely used to increase confidence in the correctness of RTL circuits during the pre-silicon design phase. Despite numerous attempts over the last decades to automate the stimuli generation based on coverage feedback, Coverage Directed Test Generation (CDG) has not found the widespread adoption that one would expect. Based on new ideas from the software testing community around coverage-guided mutational fuzz testing, we propose a new approach to the CDG problem which requires minimal setup and takes advantage of FPGA-accelerated simulation for rapid testing. We provide test input and coverage definitions that allow fuzz testing to be applied to RTL circuit verification. In addition we propose and implement a series of transformation passes that make it feasible to reset arbitrary RTL designs quickly, a requirement for deterministic test execution. Alongside this paper we provide rfuzz, a fully featured implementation of our testing methodology which we make available as open-source software to the research community. An empirical evaluation of rfuzz shows promising results on archiving coverage for a wide range of different RTL designs ranging from communication IPs to an industry scale 64-bit CPU.

https://dl.acm.org/doi/pdf/10.1145/3240765.3240842

RFUZZ: coverage-directed fuzz testing of RTL on FPGAs

It has become fairly standard in the programming-languages research world to verify functional programs in proof assistants using induction, algebraic simplification, and rewriting. In this paper, we introduce Kami, a Coq library that enables similar expressive and modular reasoning for hardware designs expressed in the style of the Bluespec language. We can specify, implement, and verify realistic designs entirely within Coq, ending with automatic extraction into a pipeline that bottoms out in FPGAs. Our methodology, using labeled transition systems, has been evaluated in a case study verifying an infinite family of multicore systems, with cache-coherent shared memory and pipelined cores implementing (the base integer subset of) the RISC-V instruction set.

https://dl.acm.org/doi/pdf/10.1145/3110268

Kami: a platform for high-level parametric hardware specification and its modular verification

Model Checking of Safety-Critical Software in the Nuclear Engineering Domain

microarchitectural models of communication fabrics present a challenge for verification. Due to the presence of deep pipelining, a large number of queues and distributed control, the state space of such models is usually too large for enumeration by protocol verification tools such as Murphi. On the other hand, we find that state-of-the-art rtl model checkers such as abc have poor performance on these models since there is very little opportunity for localization and most of the recent capacity advances in rtl model checking have come from better ways of discarding the irrelevant parts of the model. In this work we explore a new approach for verifying these models where we capture a model at a high level of abstraction by requiring that it be described using a small set of well-defined microarchitectural primitives. We exploit the high level structure present in this description, to automatically strengthen some classes of properties, in order to make them 1-step inductive, and then use an rtl model checker to prove them. In some cases, even if we cannot make the property inductive, we can dramatically reduce the number and complexity of lemmas that are needed to make the property inductive.

http://www.blif.org/~satrajit/pubs/2012_FMSD_xMAS_Inductive_Invariants.pdf

Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics

Invited Contributions.- Challenges for Formal Verification in Industrial Setting.- Distributed Verification: Exploring the Power of Raw Computing Power.- FMICS.- An Easy-to-Use, Efficient Tool-Chain to Analyze the Availability of Telecommunication Equipment.- "To Store or Not To Store" Reloaded: Reclaiming Memory on Demand.- Discovering Symmetries.- On Combining Partial Order Reduction with Fairness Assumptions.- Test Coverage for Loose Timing Annotations.- Model-Based Testing of a WAP Gateway: An Industrial Case-Study.- Heuristics for ioco-Based Test-Based Modelling.- Verifying VHDL Designs with Multiple Clocks in SMV.- Verified Design of an Automated Parking Garage.- Evaluating Quality of Service for Service Level Agreements.- Simulation-Based Performance Analysis of a Medical Image-Processing Architecture.- Blasting Linux Code.- A Finite State Modeling of AFDX Frame Management Using Spin.- UML 2.0 State Machines: Complete Formal Semantics Via core state machine.- Automated Incremental Synthesis of Timed Automata.- SAT-Based Verification of LTL Formulas.- jmle: A Tool for Executing JML Specifications Via Constraint Programming.- Goanna-A Static Model Checker.- PDMC.- Parallel SAT Solving in Bounded Model Checking.- Parallel Algorithms for Finding SCCs in Implicitly Given Graphs.- Can Saturation Be Parallelised?.- Distributed Colored Petri Net Model-Checking with Cyclades.

Formal Methods : Applications and Technology : 11th International Workshop, FMICS 2006 and 5th International Workshop, PDMC 2006, Bonn, Germany, August 26-27, and August 31, 2006 : revised selected papers

Formal verification of arithmetic datapaths has been part of the estab- lished methodology for most Intel processor designs over the last years, usually in the role of supplementing more traditional coverage oriented testing activities. For the recent Intel Core TM i7 design we took a step further and used formal verification as the primary validation vehicle for the core execution cluster, the component responsible for the functional behaviour of all microinstructions. We applied symbolic simulation based formal verification techniques for full data- path, control and state validation for the cluster, and dropped coverage driven testing entirely. The project, involving some twenty person years of verification work, is one of the most ambitious formal verification efforts in the hardware industry to date. Our experiences show that under the right circumstances, full formal verification of a design component is a feasible, industrially viable and competitive validation approach.

Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation.

Formal verification of arithmetic datapaths has been part of the established methodology for most Intel processor designs over the last years, usually in the role of supplementing more traditional coverage oriented testing activities. For the recent Intel$^{\tiny\circledR}$ CoreTM i7 design we took a step further and used formal verification as the primary validation vehicle for the core execution cluster, the component responsible for the functional behaviour of all microinstructions. We applied symbolic simulation based formal verification techniques for full datapath, control and state validation for the cluster, and dropped coverage driven testing entirely. The project, involving some twenty person years of verification work, is one of the most ambitious formal verification efforts in the hardware industry to date. Our experiences show that under the right circumstances, full formal verification of a design component is a feasible, industrially viable and competitive validation approach.

/pdf/replacing-testing-with-formal-verification-in-intel-1f064aq4ei.pdf

Replacing Testing with Formal Verification in Intel$^{\scriptsize\circledR}$ CoreTM i7 Processor Execution Engine Validation

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Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation.

Replacing Testing with Formal Verification in Intel$^{\scriptsize\circledR}$ CoreTM i7 Processor Execution Engine Validation