Dynamically Programmable Gate Arrays (DPGAs) are programmable arrays which allow the strategic reuse of limited resources. In so doing, DPGAs promise greater capacity, and in some cases higher performance, than conventional programmable device architectures where all array resources are dedicated to a single function for an entire operational epoch. This paper examines several usage patterns for DPGAs including temporal pipelining, utility functions, multiple function accommodation, and state-dependent logic. In the process, it offers insight into the application and technology space where DPGA-style reuse techniques are most beneficial.

DPGA Utilization and Application

Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing

This study describes a digitally controlled power factor correction (PFC) system based on two interleaved boost converters operating with pulsewidth modulation (PWM). Both converters are independently controlled by an inner control loop based on a discrete-time sliding-mode (SM) approach that imposes loss-free resistor (LFR) behavior on each cell. The switching surface implements an average current-mode controller so that the power factor (PF) is high. The SM-based digital controller is designed to operate at a constant switching frequency so that the interleaving technique, which is recommended for ac–dc power conversion systems higher than 1 kW, can be readily applied. An outer loop regulates the output voltage by means of a discrete-time proportional–integral (PI) compensator directly obtained from a discrete-time small-signal model of the ideal sliding dynamics. The control law proposed has been validated using numerical simulations and experimental results in a 2-kW prototype.

Interleaved Digital Power Factor Correction Based on the Sliding-Mode Approach

It has been shown that FPGAs could outperform high-end microprocessors on floating-point computations thanks to massive parallelism. However, most previous studies re-implement in the FPGA the operators present in a processor. This conservative approach is relatively straightforward, but it doesn't exploit the greater flexibility of the FPGA. We survey the many ways in which the FPGA implementation of a given floating-point computation can be not only faster, but also more accurate than its microprocessor counterpart. Techniques studied here include custom precision, mixing and matching fixed- and floating-point, specific accumulator design, dedicated architectures for coarser operators implemented as software in processors (such as elementary functions or Euclidean norms), operator specialization such as constant multiplication, and others. The FloPoCo project (http://www.ens-lyon.fr/LIP/Arenaire/Ware/FloPoCo/) aims at providing such non-standard operators. As a conclusion, current FPGA fabrics could be enhanced to improve floating-point performance. However, these enhancements should not take the form of hard FPU blocks as others have suggested. Instead, what is needed is smaller building blocks more generally useful to the implementation of floating-point operators, such as cascadable barrel shifters and leading zero counters

/pdf/when-fpgas-are-better-at-floating-point-than-microprocessors-2e3jy2frh5.pdf

When FPGAs are better at floating-point than microprocessors

Synchronous distance education can partner students and professors from different geographic or cultural regions, allowing them to share and learn from each other. Technology must support the sharing of ideas and materials. Using an iterative design approach, we investigated challenges in synchronous distance learning environments through observation of masters-level courses connecting two learning sites. Through observations, interviews, and surveys we learned of two major challenges: (1) low-quality audio/video makes interaction difficult; and, (2) presentation technologies in distance learning environments make extemporaneous teaching difficult. We developed and deployed a new distance learning system using Internet based video conferencing and a pen computer based presentation system. We studied system use in a masters level course. Analysis of qualitative data (observation notes, surveys, interview transcripts) collected in the course suggest that technological interruptions increased the feeling of separation between the sites, while the integration of natural handwriting with slides increased flexibility and was perceived positively by students and instructors.

Videoconferencing and presentation support for synchronous distance learning

This work explores the feasibility of implementing a floating-point exponentiation unit on reconfigurable computing systems. A table-driven exponentiation unit was implemented using synthesizable VHDL. The project included creating pipelined submodules for implementing basic IEEE-754 single precision operations such as addition, multiplication, and division by 32. These modules were then linked together to form the overall unit. The designs were synthesized, placed and routed. Results indicate that today's FPGAs are well suited for this operation.

FPGA-based implementation of a robust IEEE-754 exponential unit

This paper introduces a design process for a R-S-T digital controller for a power factor correction circuit (PFC). This method is based on pole placement via R-S-T polynomials. The design is based on the desired time domain specification of the current and voltage loops of a PFC presented as a discretized second order s domain transfer function for voltage and current loops. The voltage and current loop polynimials are designed to achieve the same behavior as in the s domain. Overall performance of both digital controller and its analog counterpart for PFC are investigated based on the effect of a step variation in output current, step variation and tracking of the reference voltage, and the quality of the reference current and its tracking. Furthermore, errors in the parameters identification are also taken into consideration to test the robustness of both controllers. The results confirm that digital R-S-T based controllers are able to be used for high performance PFC converters.

Digital Controller for a Boost PFC Converter in Continuous Conduction Mode

A Distance Education Course In Computer Engineering At Nc State University

The coronavirus (COVID-19) has spread quickly across the nation with a disproportionate impact on Black Americans. Many college-aged students receive their COVID-19-related information through social media and television even though research suggests that social media sources are more likely to be incorrect. Some students report trusting these sources over government sources such as the CDC and WHO. The purpose of this study was to understand Historically Black College and University (HBCU) students’ COVID-19 knowledge, sources of information, and planned precautions. There were 21 in-depth interviews conducted with students attending a large southern HBCU during Spring 2020. Themes regarding knowledge included the following: it is a flu-like condition, it has international roots, there is inaccurate and changing information, and it is a pandemic. Themes regarding sources included: the news, US government and related officials, social media, interactions with family, and other social interactions. Themes regarding severity included the following: statistics, a distrust for hospital reporting, a belief that COVID-19 deaths were conflated with baseline health, peer influence, and familial influence. Themes regarding precautions included the following: proper mask use, hand washing/ sanitizing, avoiding large crowds/small crowds only, physical distancing, COVID-19 testing/symptom monitoring, and COVID-19 vaccination. 

/pdf/navigating-a-pandemic-a-qualitative-study-of-knowledge-1bxwjt7z.pdf

Navigating a Pandemic: A Qualitative Study of Knowledge, Sources of Information, and COVID-19-Related Precautions Taken by HBCU Students

In this paper, we present a pipelined, high throughput single precision floating point implementation of the exponential function with a latency of 19 cycles. We also present the Application Specific Processor (ASP), a multiple memory architecture that increases memory bandwidth and overall performance of a computationally intensive application. The exponential function hardware unit is used as a function core or arithmetic unit of the ASP. Our experimental results show that executing a hardware implementation of the exponential function on a Field Programmable Gate Array (FPGA) is significantly faster than executing a software implementation on a multi-core processor. While the maximum clock rate of our FPGA board (200 MHz) is an order-of-magnitude slower than our multi-core processor (3.4 GHz), the FPGA-based hardware implementation of the exponential function is 29X and 8X faster than the multi-core processor-based software implementation and OpenMP implementation respectively.

An FPGA-based Application-Specific Processor for Implementing the Exponential Function

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