Microsystems using three-dimensional integration and TSV technologies: Fundamentals and applications

We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interconnects process and characterization. 3D packaging is presented up to the successful structural test and characterization of the demonstrator.

Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures

The reliability of metal filled through silicon vias (TSVs) will determine their suitability in the semiconductor industry. The adoption of this technology will depend strongly on the materials used for filling vias that function as vertical interconnects. Conventional materials for filling TSVs include copper and tungsten. Carbon nanotubes (CNTs) are an excellent candidate to replace or be used in conjunction with these materials due to their superior electrical and mechanical properties. Metallic CNT bundles can allow nearly unhampered transport of electrons, resulting in a low resistance interconnect capable of withstanding high current densities. The growth of CNTs with ethylene and methane precursors by thermal chemical vapor deposition has been investigated using thin films of aluminum oxide and iron as catalysts. Nickel and cobalt were investigated as well with limited success. CNT growth is followed by electrochemical deposition (ECD) of copper. Traditionally, sputtered or evaporated Cu is used as a seed layer for ECD; however, the high temperatures necessary for CNT growth made Cu an unsuitable seed layer due to migration. The authors investigated combinations of ECD seed layers and CNT catalysts on the surface of a silicon wafer to qualify the best materials for the formation of a Cu/CNT matrix. ECD of Cu was studied on as-grown and densified CNTs with a tungsten seed layer. Once the process for covering CNT bundles with copper is optimized, future work will focus on placing the materials system inside cylindrical vias formed using an inductively coupled plasma etch process.

Development of seed layer for electrodeposition of copper on carbon nanotube bundles

Through-silicon vias (TSVs) are a critical technology for three-dimensional integrated circuit technology. These through-substrate interconnects allow electronic devices to be stacked vertically for a broad range of applications and performance improvements such as increased bandwidth, reduced signal delay, improved power management, and smaller form-factors. There are many interdependent processing steps involved in the successful integration of TSVs. This article provides a tutorial style review of the following semiconductor fabrication process steps that are commonly used in forming TSVs: deep etching of silicon to form the via, thin film deposition to provide insulation, barrier, and seed layers, electroplating of copper for the conductive metal, and wafer thinning to reveal the TSVs. Recent work in copper electrochemical deposition is highlighted, analyzing the effect of accelerator and suppressor additives in the electrolyte to enable void-free bottom-up filling from a conformally lined seed metal.

https://avs.scitation.org/doi/pdf/10.1116/6.0000026

Tutorial on forming through-silicon vias

Spectroscopic analysis of ultra-thin TiN as a diffusion barrier for lithium-ion batteries by ToF-SIMS, XPS, and EELS

Study of low temperature MOCVD deposition of TiN barrier layer for copper diffusion in high aspect ratio through silicon vias

In recent years, 3D integration has become an alternative solution to the “More Moore” concept for providing circuits with higher performance or increased functionality. Via-Middle TSV is considered a reference integration scheme and requires void-free copper fill of very high aspect ratio TSVs. Metallization of such structures, in particular barrier and seed layer deposition, becomes a critical process step as barrier material to copper diffusion must provide good efficiency to copper diffusion for further integration and especially on TSV sidewalls, requiring sufficient step coverage. Ionized PVD is today widely extended from BEOL to TSV metallization. This technique has, however , several limitations for 3D integration coming from its poor step coverage in 10:1 aspect ratio features thus requiring thick material deposition to cover sidewalls which will lead to expensive process both for deposition and further CMP steps and high stress leading to adhesion issues. Considering the maturity level of the al...

Low temperature MOCVD TiN barrier deposition for high aspect ratio TSVs : A solution for 3D integration

Fan-out wafer level packaging (FO-WLP) technology is an increasingly popular solution for obtaining high level device integration with a greater I/O count, at a lower cost. In FO-WLP schemes, singulated die are embedded in epoxy mold compound (EMC). While EMC is a cost-effective material, it readily absorbs moisture, as do the polymer dielectrics used to electrically isolate adjacent metal interconnects. These materials must be degassed prior to physical vapor deposition (PVD) of under-bump metals (UBM) and redistribution layers (RDL), otherwise metal to metal interfaces can be contaminated, negatively impacting electrical performance of the device. With the low thermal budget of the EMC (<150°C), an effective degas requires low temperature and long process times that can significantly reduce throughput if using a single wafer degas approach. This paper describes a "Multi-Wafer Degas" solution under vacuum to eliminate the ""degas bottleneck" and ensure lowest contact resistance (Rc). This solution typically doubles the throughput compared with competing PVD systems, and is being used in high volume 300mm FO-WLP production. In addition, vacuum degassing is compared with atmospheric degassing techniques, with clear benefits in performance being identified for the vacuum degas approach. In addition, prior to UBM/RDL metallization, native oxide needs to be removed from exposed metal contacts. In the SPTS Sigma® fxP PVD system, ICP etch technology is used to limit the energy of ions at the wafer, and so limit the peak wafer temperature. In high density packages using multiple RDL, the upper interconnect level can present large exposed areas of metal to the pre-clean module, which can lead to a breakdown in RF coupling in ICP technology during etch. The presence of organic passivation such as PI or PBO can also lead to premature particle failures because of poor adhesion of organics to chamber furniture. This paper introduces a pre-clean etch module, designed to provide ICP 'soft etch' cleaning capability whilst overcoming the process and particle stability challenges posed by increased I/O contacts and organics. Data from systems in production will be presented, demonstrating the efficacy of the technology. The paper will show long time between chamber cleans in an ICP pre-clean module, along with low & stable Rc data. System modifications for coping with epoxy mold wafer warpage and cost reduction efforts are also discussed.

UBM/RDL Deposition by PVD for FOWLP in High Volume Production

MOCVD (Metal-Organic Chemical Vapor Deposition) copper metallization was developed on 300mm wafers, to fulfil 3D Through-Silicon Via (TSV) interconnect requirements. Using a fluorine-free organometallic precursor, the bis(dimethylamino-2-propoxy)copper (II) Cu[OCHMeCH2NMe2]2 at low temperature deposition, we developed a high purity, low stress copper film with strong adhesion to a TiN barrier layer. Argon was used as a carrier gas and H2 and/or H2O as a co-reactant. This MOCVD technique offers good conformality observed with 10μm×120μmTSVs. The thin copper seed layer was successfully integrated on 300mm wafers. A new XRD protocol was developed to characterize the copper seed layer along the TSV sidewalls, revealed higher microstructure quality, lower stressed in the case of copper film deposited by CVD compared to those deposited by i-PVD.

MOCVD Copper Metallization for High Aspect Ratios TSV 3D Integration.

In an age where we are witnessing the emergence of high power computing requirements for a variety of applications, Fan-Out Wafer Level Packaging (FO-WLP) technology is an increasingly popular solution for obtaining a high level of device integration with a greater number of I/O contacts, in a small package. First introduced for small die applications such as power management and RF transceivers, it now serves as a platform for mobile application processors. There are many different FO-WLP schemes in use, all aimed at achieving better device performance in a smaller/thinner/cheaper package. While the different schemes vary in their detail, in simple terms, they all involve embedding die in a cost-effective epoxy mold substrate with metal redistribution layers (RDL) forming the interconnects between die and bump connections.Prior to UBM/RDL metallization by physical vapor deposition (PVD), the mold substrate needs to be degassed and native oxide needs to be removed from the metal contacts, within the relatively low thermal budget imposed by the epoxy mold. Due to a lower ion energy, Inductively Couple Plasma (ICP) etch processing induces less heating and lower levels of contamination from any organics on the substrate during the removal of the oxide, than alternative “diode” plasma etching solutions. Data will be presented showing long time between chamber cleans, and how a novel in-situ pasting technique gives low & stable contact resistance.

Fan-Out Wafer Processing In The High Density Packaging Era

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