Chirag Gupta
University of California, Santa Barbara
50 Papers
173 Citations
Chirag Gupta is an academic researcher from University of California, Santa Barbara. The author has contributed to research in topics: Gallium nitride & Breakdown voltage. The author has an hindex of 13, co-authored 45 publications. Previous affiliations of Chirag Gupta include Indian Institute of Technology Kanpur & University of California.
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Papers
Comparing electrical performance of GaN trench-gate MOSFETs with a-plane and m-plane sidewall channels
Chirag Gupta,Silvia H. Chan,Cory Lund,Anchal Agarwal,Onur S. Koksaldi,Junquian Liu,Yuuki Enatsu,Yuuki Enatsu,Stacia Keller,Umesh K. Mishra +9 more
TL;DR: In this paper, a GaN trench-gate MOSFET with m-plane-oriented sidewall channels was fabricated and characterized, and it was shown that orienting the trench gate toward the mplane would allow for better on-state characteristics while maintaining similar offstate characteristics.
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First Demonstration of AlSiO as Gate Dielectric in GaN FETs; Applied to a High Performance OG-FET
TL;DR: In this article, the first demonstration of a GaN FET with aluminum silicon oxide (AlSiO) as the gate dielectric was reported, which achieved a breakdown voltage of 1.2 kV, an ON-resistance of 2.2kV, and a threshold voltage of 0.5 V (defined at $I_{\textsf {DS}} = 1\,\, \mu \text{A}$ /mm).
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Demonstration of a GaN/AlGaN Superlattice-Based p-Channel FinFET With High ON-Current
Aditya Raj,Athith Krishna,Nirupam Hatui,Chirag Gupta,Raina Jang,Stacia Keller,Umesh K. Mishra +6 more
TL;DR: In this paper, a two-step approach involving a dry etch followed by a Tetramethylammonium hydroxide (TMAH) wet etch was employed to obtain fins with minimum width of 50 nm using optical lithography.
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High breakdown voltage p–n diodes on GaN on sapphire by MOCVD
TL;DR: In this article, a decrease in the background carrier concentration and threading dislocation density with an increase in the thickness of unintentionally doped (UID) GaN grown on sapphire was demonstrated.
44
Improved Dynamic R ON of GaN Vertical Trench MOSFETs (OG-FETs) Using TMAH Wet Etch
Dong Ji,Wenwen Li,Anchal Agarwal,Silvia H. Chan,Jeffrey Haller,Davide Bisi,Michelle Labrecque,Chirag Gupta,Bill Cruse,Rakesh K. Lal,Stacia Keller,Umesh K. Mishra,Srabanti Chowdhury +12 more
TL;DR: This letter reports on the dynamic performance of large-area GaN vertical trench MOSFETs fabricated on bulk GaN substrates, which demonstrated excellent DC performance and damage to the trench sidewalls caused by RIE dry etching led to poor dynamic performance.
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